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2003-10-16 by sudha srinivasan
Dear all, Does the SPI bus automatically assert the chip select(CS/) if one byte has to be transmitted to an external device? In other words, Is it enough if we just enable the SPE bit in the SPCR1 register to transmit one byte of data which means that the setting of SPE bit will select the chip and deselect as soon as one byte is transmitted. Kindly respond, Sudha
2003-10-16 by jeffrey.tenney@gm.com
Sudha,
The QSPI is capable of performing an 8-bit transfer like the one you
describe.
First, make sure you set up the corresponding byte in the command RAM
correctly:
CONT = 0 to insure peripheral is deselected after transfer,
BITSE = 0 to exchange only 8 bits,
PCSn = specific to your desired chip select. (For "automatic" CS
assertion->negation)
Don't forget to set NEWQP and ENDQP (in SPCR2) to the same address as the
byte you want to send, and you should be all set.
Jeff
"sudha srinivasan" <sudha_sri@...>
10/15/2003 11:54 PM
Please respond to 68300
To: "68332 \(E-mail\)" <68300@yahoogroups.com>
cc: Subject: [68300] QSPI of M68332 Dear all, Does the SPI bus automatically assert the chip select(CS/) if one byte has to be transmitted to an external device? In other words, Is it enough if we just enable the SPE bit in the SPCR1 register to transmit one byte of data which means that the setting of SPE bit will select the chip and deselect as soon as one byte is transmitted. Kindly respond, Sudha --------------------------------------------------- To unsubscribe from this group, send an email to: 68300-unsubscribe@yahoogroups.com To learn more about Motorola Microcontrollers, please visit http://www.motorola.com/mcu Your use of Yahoo! Groups is subject to http://docs.yahoo.com/info/terms/ [Non-text portions of this message have been removed]
2003-10-16 by Melear Charles-rdph40
Sudha, I assume that you are talking about the QSPI. When you are going to transmit data, you first load the data into the transmit queue. Associated with each entry in the transmit data RAM is a byte in the Command RAM. The Command RAM specifies which of the 4 SPI chip select pins will assert. The PCS lines are under the control of the Port Data Register and Port Data Direction Register when the SPE bit is cleared. When your software sets the SPE bit, the PCS lines are under the control of the QSPI. So, when you enable the QSPI, the PSC lines will assert automatically according to how you program the Command RAM. Regards, Charlie
-----Original Message----- From: sudha srinivasan [mailto:sudha_sri@...] Sent: Thursday, October 16, 2003 1:54 AM To: 68332 \(E-mail\) Subject: [68300] QSPI of M68332 Dear all, Does the SPI bus automatically assert the chip select(CS/) if one byte has to be transmitted to an external device? In other words, Is it enough if we just enable the SPE bit in the SPCR1 register to transmit one byte of data which means that the setting of SPE bit will select the chip and deselect as soon as one byte is transmitted. Kindly respond, Sudha Yahoo! Groups Sponsor ADVERTISEMENT <http://rd.yahoo.com/M=244522.3707890.4968055.1261774/D=egroupweb/S=1706554205:HM/A=1595055/R=0/SIG=124j83ehr/*http://ashnin.com/clk/muryutaitakenattogyo?YH=3707890&yhad=1595055> Click Here! <http://us.adserver.yahoo.com/l?M=244522.3707890.4968055.1261774/D=egroupmail/S=:HM/A=1595055/rand=878882341> --------------------------------------------------- To unsubscribe from this group, send an email to: 68300-unsubscribe@yahoogroups.com To learn more about Motorola Microcontrollers, please visit http://www.motorola.com/mcu <http://www.motorola.com/mcu> Your use of Yahoo! Groups is subject to the Yahoo! Terms of Service <http://docs.yahoo.com/info/terms/> . [Non-text portions of this message have been removed]