68300

Sudha,
 
I assume that you are talking about the QSPI.
 
When you are going to transmit data, you first load the data into the transmit queue.  Associated with each entry in the transmit data RAM is a byte in the Command RAM.  The Command RAM specifies which of the 4 SPI chip select pins will assert.
 
The PCS lines are under the control of the Port Data Register and Port Data Direction Register when the SPE bit is cleared.  When your software sets the SPE bit, the PCS lines are under the control of the QSPI.
 
So, when you enable the QSPI, the PSC lines will assert automatically according to how you program the Command RAM.
 
Regards,
 
Charlie

-----Original Message-----
From: sudha srinivasan [mailto:sudha_sri@...]
Sent: Thursday, October 16, 2003 1:54 AM
To: 68332 \(E-mail\)
Subject: [68300] QSPI of M68332


Dear all,

Does the SPI bus automatically assert the chip select(CS/) if one byte has
to be transmitted to an external device?
In other words,  Is it enough if we just enable the SPE bit in the SPCR1
register to transmit one byte of data which means that
the setting of SPE bit will select the chip and deselect as soon as one byte
is transmitted.


Kindly respond,
Sudha



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