Ned Konz wrote: > On Apr 26, 2006, at 12:03 PM, Peter Harrison wrote: > >> Hi >> >> I have an optical sensor. It triggers an emitter and reads a response >> from a photodiode and amplifier. after firing the emitter, I wait >> until >> the amplifier has had time to reach a stable output - say 5us - then I >> initiate an ADC conversion. >> >> Now, If I turn off the emitter too soon, the ADC result is >> decreased so >> my question is: How long should I keep the signal present at the ADC >> input to allow the internal sample and hold capacitor to charge? >> >> According to the (ATMEGA32) datasheet, the S/H capacitor has a >> value of >> 14pF but the series resistance of the multiplexer is shown as >> 1..100kOhm. This seems a bit of a large range. Time constants could be >> up to 1.4us requiring that I wait as long as 7us or so to charge the >> capacitor. The source impedance is an op-amp output so it should not >> have any effect to speak of. The sheet also describes the sampling >> time >> as negligible. Seems like a new, optimistic definition of the word >> to me. >> > The 7usec is not out of line, considering that the sample/hold is > sampling until 1.5 sample clocks after asserting ADSC (which is, at > best, 7.5usec given that 200KHz is the max clock for 10 bit > conversions). Ah... We have a thing at work where the act of asking the question seems to help the brain formulate a solution. I had overlooked the 1.5 clocks bit and now I have read the sheet again in the light of that I think I can substantially improve things. For example, since I am likely to have to wait 7us anyway for a sample and hold action (with a 200kHz ADC clock) then I might as well trigger a conversion at the same time as the emitter is fired. The sensor amplifier will have reached its output level by the time the ADC does the sample anyway. The second delay seems to be redundant. That will halve the time spent in the sensor interrupt. (in the original post, I said I waited 1us for a sample when I should have written 10us) I could still do with knowing how long the sample takes though. If the series resistor really is only 1k, I can motor on a bit more. Perhaps I will have to do some tests and vary the delay to see the effect on the response. > Have you considered "free-running" mode? > Not really appropriate I think. There are four channels, each must be fired and read individually in sequence and a complete set must be done every millisecond. That seems to require the triggered measurements. Pete Harrison
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Re: [AVR-Chat] ADC sample time
2006-04-27 by Peter Harrison
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