AVR-Chat

Jim;

Yeah, I know it is a bit much, I had forgotten about the sei 
instruction, which is something that hasn't existed on processors i have 
worked with in the past.

Yes, I have the interrupts enabled (at least, if I understood the data 
sheet on how to do that, I do), and yes (again, contingent upon my 
correct understanding of the data sheet), I have the timer control bits 
set for the performance I wish.  This is why I am so confuzzled.

tom

Jim Wagner wrote:
>
> Tom
>
> The only bit that has anything to do with interrupts in the
> SREG is Bit7:GlobalInterruptEnable. Are you doing all that
> to try to set and clear Bit7?
>
> It would seem like it OUGHT to execute an ISR. Do you have
> the corresponding bits set in the timer? For a Mega16, its
> the TIMSK (Timer Mask Register) and, after the timer event
> happens, a bit is set in the TIFR (Timer Interrupt Flag
> Register). This latter bit will be cleared when the ISR
> executes.
>
> J
>
>