AVR-Chat

Tom -

A technique I have used to debug timers is to temporarily
set up the timer so that the interrupt happens in a
relatively few clock cycles. This can be done by using the
minimum clock prescale, a small compare value, etc. Then, I
manually steep through the program and when it gets close
to the point where I expect the action, I view the
registers (to the left of the code window in Studio). Then
I watch exactly what happens. Usually, I find that
something fairly simple does not happen the way I expected.
Then, I read the docs to see what I overlooked.

Jim

On Sat, 06 Jan 2007 10:32:33 -0600
 Thomas Keller <tjkeller1@alltel.net> wrote:
> Jim;
> 
> Yeah, I know it is a bit much, I had forgotten about the
> sei 
> instruction, which is something that hasn't existed on
> processors i have 
> worked with in the past.
> 
> Yes, I have the interrupts enabled (at least, if I
> understood the data 
> sheet on how to do that, I do), and yes (again,
> contingent upon my 
> correct understanding of the data sheet), I have the
> timer control bits 
> set for the performance I wish.  This is why I am so
> confuzzled.
> 
> tom
> 
> Jim Wagner wrote:
> >
> > Tom
> >
> > The only bit that has anything to do with interrupts in
> the
> > SREG is Bit7:GlobalInterruptEnable. Are you doing all
> that
> > to try to set and clear Bit7?
> >
> > It would seem like it OUGHT to execute an ISR. Do you
> have
> > the corresponding bits set in the timer? For a Mega16,
> its
> > the TIMSK (Timer Mask Register) and, after the timer
> event
> > happens, a bit is set in the TIFR (Timer Interrupt Flag
> > Register). This latter bit will be cleared when the ISR
> > executes.
> >
> > J
> >
> >
> 

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