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Re: [lpc2000] UART TX FIFO and INTs problem - SOLVED

2004-02-22 by Bill Knight

The kernel of a preemptive RTOS might want to.

Bill



On Sun, 22 Feb 2004 14:32:55 -0500, Robert Adsett wrote:

At 02:22 PM 2/22/04 -0500, you wrote:
>At 10:13 AM 2/22/04 -0600, you wrote:
> >As a side note.  The disabling and restoring of the global interrupt
> >flag in the cpsr can has a similar problem.

><snip>

> >For more info on this, Atmel has
> >an APP note discribing it on their web site in the AT91 ARM7 section.

>Thanks for the pointer.

I just had a chance to read the app note (I presume this is the one 
http://www.atmel.com/dyn/resources/prod_documents/DOC1156.PDF) and it 
appears to be warning about faults that can happen when using a style of 
code I would consider very error prone to begin with.  Unless I'm missing 
something (I've only had a little while to consider it) the only time a 
problem occurs if an interrupt routine actually modifies the cpu status of 
the interrupted code.  What would ever prompt anyone to do that in the 
first place?

Robrt

" 'Freedom' has no meaning of itself.  There are always restrictions,
be they legal, genetic, or physical.  If you don't believe me, try to
chew a radio signal. "

                         Kelvin Throop, III





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