Lpc2000

Hi guys,

I've done some more testing with some of the different values 
proposed for the PLL and MAM, but the problems continue.  From this I 
suppose that the problem with the communication may be in the UART 
settings rather than the PLL or MAM settings.

But the problem of the last pin clear is still strange...it must be 
something setting or affect I've overlooked.  Is the operation of the 
processor so sensitive to these changes?

I will do some further study of the PLL, MAM and UART, as well as my 
code and see what I can uncover.

Thanks for the help so far.

Karl
 

--- In lpc2000@yahoogroups.com, "rtstofer" <rstofer@...> wrote:
> > > also look at the support routines in the newlib-lpc lib for an 
> > example that 
> > > takes the crystal frequency and desired operating frequency as 
> > inputs and 
> > > set the PLL registers accordingly.  That might give you a 
double 
> > check on 
> > > your values.
> > > 
> > > Robert
> 
> It is worth noting that in "MAM USAGE NOTES" on page 59 or the
> September 17, 2003 User Manual, for a speed above 40 MHz, 3 CCLKs 
are
> proposed as the MAMTIM value.  Just 'proposed', mind you.
> 
> Your MAMTIM value is probably too small.  I have had good success 
with
> a value of 4 but I haven't tried 3.
> 
> VPBDIV can be 0x00 if you wish.  I use 0x01 so the VPB bus clock is
> the same as the processor clock.
> 
> Richard
>