Lpc2000

In using the serial port (UART0) I found that simply enabling the 
THRE interrupt does not cause an interrupt to be asserted.  
Apparently only when the TX FIFO transistions to empty does the 
interrupt get asserted.  I know the VIC and UART0 hardware are set-
up correctly since if I manually load the first byte into the THR I 
do get a THRE interrupt when the byte is transmitted.  Has anyone 
else noticed this or am I doing something wrong?
James