Lpc2000

In using the serial port (UART0) I found that simply enabling the 
THRE interrupt does not cause an interrupt to be asserted.  
Apparently only when the TX FIFO transistions to empty does the 
interrupt get asserted.  I know the VIC and UART0 hardware are set-
up correctly since if I manually load the first byte into the THR I 
do get a THRE interrupt when the byte is transmitted.  Has anyone 
else noticed this or am I doing something wrong?
James

At 06:46 PM 11/11/04 +0000, you wrote:
>In using the serial port (UART0) I found that simply enabling the
>THRE interrupt does not cause an interrupt to be asserted.
>Apparently only when the TX FIFO transistions to empty does the
>interrupt get asserted.  I know the VIC and UART0 hardware are set-

That is what it is supposed to do.  There is no way to tell if the FIFO is 
partially full so THRE fires when it is empty and you can then stuff up to 
16 bytes into the FIFO.

Robert

" 'Freedom' has no meaning of itself.  There are always restrictions,
be they legal, genetic, or physical.  If you don't believe me, try to
chew a radio signal. "

                         Kelvin Throop, III

Robert,
The FIFO IS empty (I haven't yet loaded anything into the FIFO).  
But no THRE interrupt.  Did you mean to say this is correct 
behavior?  (Again, if I manually load the first byte into the FIFO, 
from then on the interrupt works great.)
James


--- In lpc2000@yahoogroups.com, Robert Adsett <subscriptions@a...> 
wrote:
> At 06:46 PM 11/11/04 +0000, you wrote:
> >In using the serial port (UART0) I found that simply enabling the
> >THRE interrupt does not cause an interrupt to be asserted.
> >Apparently only when the TX FIFO transistions to empty does the
> >interrupt get asserted.  I know the VIC and UART0 hardware are 
set-
> 
> That is what it is supposed to do.  There is no way to tell if the 
FIFO is 
> partially full so THRE fires when it is empty and you can then 
stuff up to 
> 16 bytes into the FIFO.
> 
> Robert
> 
> " 'Freedom' has no meaning of itself.  There are always 
restrictions,
> be they legal, genetic, or physical.  If you don't believe me, try 
to

> chew a radio signal. "
> 
>                          Kelvin Throop, III

At 06:57 PM 11/11/04 +0000, you wrote:
>The FIFO IS empty (I haven't yet loaded anything into the FIFO).
>But no THRE interrupt.  Did you mean to say this is correct
>behavior?  (Again, if I manually load the first byte into the FIFO,
>from then on the interrupt works great.)

Sorry, I misunderstood, I had thought you were already transmitting.  That 
is correct behaviour as well.  It's meant to keep you from going into an 
infinite transmission interrupt loop if you have nothing to transmit.  You 
have to 'prime the pump' by placing at least one byte in the transmit FIFO 
to start.  If you ever run out of bytes to transmit you have to do it again.

Robert

" 'Freedom' has no meaning of itself.  There are always restrictions,
be they legal, genetic, or physical.  If you don't believe me, try to
chew a radio signal. "

                         Kelvin Throop, III

IIRC that is what I found also.

-Bill Knight
http://www.theARMPatch.com


On Thu, 11 Nov 2004 18:46:22 -0000, jamesasteres wrote:

In using the serial port (UART0) I found that simply enabling the 
THRE interrupt does not cause an interrupt to be asserted.  
Apparently only when the TX FIFO transistions to empty does the 
interrupt get asserted.  I know the VIC and UART0 hardware are set-
up correctly since if I manually load the first byte into the THR I 
do get a THRE interrupt when the byte is transmitted.  Has anyone 
else noticed this or am I doing something wrong?
James

This behavior is correct indeed. If you want to you can check the 
FreeRTOS (www.freertos) serial driver. There you will see that it is 
also implemented to operate according to the behavior you described.

Regards,
Teun van de Berg


--- In lpc2000@yahoogroups.com, Robert Adsett <subscriptions@a...> 
wrote:
> At 06:46 PM 11/11/04 +0000, you wrote:
> >In using the serial port (UART0) I found that simply enabling the
> >THRE interrupt does not cause an interrupt to be asserted.
> >Apparently only when the TX FIFO transistions to empty does the
> >interrupt get asserted.  I know the VIC and UART0 hardware are set-
> 
> That is what it is supposed to do.  There is no way to tell if the 
FIFO is 
> partially full so THRE fires when it is empty and you can then 
stuff up to 
> 16 bytes into the FIFO.
> 
> Robert
> 
> " 'Freedom' has no meaning of itself.  There are always 
restrictions,
> be they legal, genetic, or physical.  If you don't believe me, try 
to

> chew a radio signal. "
> 
>                          Kelvin Throop, III