Lpc2000

At 06:46 PM 11/11/04 +0000, you wrote:
>In using the serial port (UART0) I found that simply enabling the
>THRE interrupt does not cause an interrupt to be asserted.
>Apparently only when the TX FIFO transistions to empty does the
>interrupt get asserted.  I know the VIC and UART0 hardware are set-

That is what it is supposed to do.  There is no way to tell if the FIFO is 
partially full so THRE fires when it is empty and you can then stuff up to 
16 bytes into the FIFO.

Robert

" 'Freedom' has no meaning of itself.  There are always restrictions,
be they legal, genetic, or physical.  If you don't believe me, try to
chew a radio signal. "

                         Kelvin Throop, III