Lpc2000

At 08:02 PM 11/18/04 +0000, you wrote:
> > >Should I enable the FIFOs (write 1 to U0FCR) before running the
> > >interrupts? I seem to be getting by without this up until this
>point.
> >
> > I don't see why that would eliminate the problem.  Worse it might
>hide it
> > so that it showed up later under less benign conditions.
> >
>
>Good news...I got communication running alot better after enabling
>FIFOs (U0FCR = 1) at startup. So far, no Rx & Tx glitches yet. Try
>doing the same to see what happens.

That rather worries me.  I will give it try and see what it does on my code 
though (I've got a few other items to take care of first).  I place it in 
the same category as my read-IIR-only-once-per-interrupt 'fix' though.  I 
strongly suspect it's only masking temporarily whatever the underlying 
cause is.

I suspect there is something similar going on here as happens with the SPI 
and the timers.  We've now got two independent reports of missing 
interrupts on the UART with no clear source of the problem.

Robert


" 'Freedom' has no meaning of itself.  There are always restrictions,
be they legal, genetic, or physical.  If you don't believe me, try to
chew a radio signal. "

                         Kelvin Throop, III