Lpc2000

Robert Adsett wrote:

>But to how low a voltage do they operate.  A good reset chip will provide a 
>low output down to about 0.8V.  It would be a real problem if the 8 pin 
>micro's brown-out circuitry kicked in and caused the reset line to float at 
>say 1.7V.  I suppose you could reverse the problem and use a resistive 
>pulldown and override that with a positive output but then you need to know 
>how high a resistance you can use and still provide a reset voltage 
>(particularly at low VCC), is that specced anywhere?
>

Yes, I always use a resistive pulldown for that very reason, but why do 
worry about how high a resistance? Granted, I usually use between 10K 
and 100K which is never a problem with a CMOS input. There are in fact 
two CMOS inputs in this state, the reset micro's reset output(input), 
and the main reset input. The reset line can only see a low as there is 
no voltage source from the reset micro even down to very low voltages.

I've scoped this before under all kinds of nasty power up/downs. A 
circuit that is intrinsically in reset unless all systems are go is a 
very safe way to handle the reset.

This way works extremely well and permits ISP/reset over remote links. 
Well, that's the way I handle things in this area and others may have 
their own ideas. But that's what these discussions are good for, it's a 
real melting pot of ideas and experiences. Although.... there's the 
occasional flame that shoots up and chars a few bits too... :)

*Peter*



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