I am new to the ARM, but I know from my extensive AVR experience that removing
the "volatile" directive can lead to bad code. Is this a problem with what
you are proposing for the ARM?
Without the volatile direction GCC may optimize access to the hardware
registers more times, or less times that you expect. You can end up clearing
bits unintentionally this way. For example a status register read may clear
bits.
On Wednesday 25 May 2005 11:57 am, Robert Adsett wrote:
> At 11:37 AM 5/25/05 -0400, Brett Delmage wrote:
> >#define REG(addr) (*(volatile unsigned long *)(addr))
> >#define REG8(addr) (*(volatile char *)(addr))
...
> I haven't done a comparison of code generation but I use ld in combination
> with gcc for this.
...
> PROVIDE( MAMCR = 0xE01FC000);
> PROVIDE( MAMTIM = 0xE01FC004);
...
> MAMCR = (unsigned char)ctrl; /*lint !e930 cast from enum */
> MAMTIM = (unsigned char)cycle_time;
--
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Re: [lpc2000] accessing SPI registers
2005-05-26 by Bob Paddock
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