I had similar experiences with GPIO and the external memory controller on a LPC2292. I found out that in this case, it is possible for a read to start on the external memory controller before a write to the GPIO is finished. Don't know if this is the same problem because you are only using GPIO, maybe you are using both port0 and port1??? Try writing the RD_low twice, that way the first write must be finished before the second can begin, the second write does not change anything, so the read is occuring when the outputs are in the right state. Richard Duits Michael Anburaj wrote: > Hi, > > I have got the CS8900A talking to the LPC2106 in 8bit > mode. Strange things are happening > > Without any delay (without additional delay added in > code) in the Rd & Wr cycles, repeated reads result in > random values. > Then I added delay to stretch the RD_low > > RD_low > delay > Read_Data > RD_hi > > With this I get consistent reads, but the bytes seem > to be swapped. > > For instance, when read 0 (ProductID), read from Data0 > == 0x63 & Data1 == 0x0e > yields 0x0e63, but it should have been 0x630e > > Similarly I get 0xd000 when I read SelfST. With > different delay values I get 0x0000 for SelfST or > 0x6363 for ProdID. > > Can someone let me know what delays are required & > where, it will be great! > > Thanks a lot, > -Mike. > > > > __________________________________ > Yahoo! Music Unlimited > Access over 1 million songs. Try it free. > http://music.yahoo.com/unlimited/ > > ------------------------------------------------------------------------ > YAHOO! GROUPS LINKS > > * Visit your group "lpc2000 > <http://groups.yahoo.com/group/lpc2000>" on the web. > > * To unsubscribe from this group, send an email to: > lpc2000-unsubscribe@yahoogroups.com > <mailto:lpc2000-unsubscribe@yahoogroups.com?subject=Unsubscribe> > > * Your use of Yahoo! Groups is subject to the Yahoo! Terms of > Service <http://docs.yahoo.com/info/terms/>. > > > ------------------------------------------------------------------------ >
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Re: [lpc2000] LPC2106 & CS8900A -- delay needed in Rd/Wr?
2005-10-16 by Richard Duits
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