Lpc2000

Hi,

I use the LPC2103 microprocessor and I like it very much.
I was wondering if the usage of barrel shifter in the ARM instruction
set eats up more cycles.
ARM datasheets mention the SHIFT(Rs) eats up one more cycle, though
I'm not sure if they mean that shifting by a register takes a cycle,
but shifting by a const is free, or any shift takes a cycle.

MOV r0, r1, ASR #16 ; 1 Cycle ? 2 Cycles ?
MOV r0, r1, ASR r2  ; 1 Cycle ? 2 Cycles ? 3 Cycles ?

Thanks in advance,
MB

MB wrote:
> I use the LPC2103 microprocessor and I like it very much.
> I was wondering if the usage of barrel shifter in the ARM instruction
> set eats up more cycles.
> ARM datasheets mention the SHIFT(Rs) eats up one more cycle, though
> I'm not sure if they mean that shifting by a register takes a cycle,
> but shifting by a const is free, or any shift takes a cycle.

Good question, I had to check the extra cycle thing myself. The ARM uses 
a barrel shifter which means that it can perform multi-bit shifts in one 
operation, so it doesn't matter whether you specify 1 or 31 bits, or 
whether the operand is a register or a constant. The shift operation 
takes take one extra cycle (Internal cycle) over a normal data operation 
though.

 >
 > MOV r0, r1, ASR #16 ; 1 Cycle ? 2 Cycles ?
 > MOV r0, r1, ASR r2  ; 1 Cycle ? 2 Cycles ? 3 Cycles ?

The shift operand is taken either from the instruction field or read 
directly from a register so it makes no difference to the instruction 
processing as both operands are "on-hand".

MOV r0, r1, ASR #16  ; 2 cycles
MOV r0, r1, ASR r2  ; 2 cycles

The only 3 cycle data operations are when a shift is specified and r15 
is the destination.

*Peter*

The ARM7TDMI-S TRM says something different:

Data processing Single-cycle                  +S
Data processing Register-specified shift      +I +S
Data processing R15 destination               +N +2S
Data processing R15, register-specified shift +I +N +2S

Only a shift by register (ASR r2) requires an additional datapath cycle. The 
immediate variant (ASR #16) is executed in a single cycle. If the PC is the 
destination register, two additional cycles are required, to refill the 
pipeline.

Regards,

Dominic

On Saturday 06 May 2006 10:43, Peter Jakacki wrote:
> Good question, I had to check the extra cycle thing myself. The ARM uses
> a barrel shifter which means that it can perform multi-bit shifts in one
> operation, so it doesn't matter whether you specify 1 or 31 bits, or
> whether the operand is a register or a constant. The shift operation
> takes take one extra cycle (Internal cycle) over a normal data operation
> though.
>
>  > MOV r0, r1, ASR #16 ; 1 Cycle ? 2 Cycles ?
>  > MOV r0, r1, ASR r2  ; 1 Cycle ? 2 Cycles ? 3 Cycles ?
>
> The shift operand is taken either from the instruction field or read
> directly from a register so it makes no difference to the instruction
> processing as both operands are "on-hand".
>
> MOV r0, r1, ASR #16  ; 2 cycles
> MOV r0, r1, ASR r2  ; 2 cycles
>
> The only 3 cycle data operations are when a shift is specified and r15
> is the destination.
>
> *Peter*