Lpc2000

Hi,

I have been developing software to perform SPI transfers.  I am using 
a logic analyzer to examine the SCLK, MOSI, MISO and gpio signals.  
The board I am using is an IAR Kickstart card with a 14.7MHz clock. 
The first thing that I found was that if I set the SOSPCCR counter 
field to 8, I got a 460.8KHz SCLK signal and everything looked 
correct.  If I changed the SOSPCCR counter to 4, I got a 921KHz SCLK 
signal but the data on MOSI signal shifted so that the correct value 
was not present on the rising edge of SCLK. CPHA and CPOL are both 
zero.  At higher SCLK rates I got 9 positive pulses on SCLK instead 
of 8. Is the maximum usable SCLK limited to somewhere between 460KHz 
and 921KHz or is something wrong.

I use a GPIO pin (P0_16) for a CS signal.  I found that if I execute 
the following code,

        IOCLR_bit.P0_16 = 1;
        S0SPDR_bit.DATA=*ptr;
        ptr++;
        while(!S0SPSR_bit.SPIF);
        IOSET_bit.P0_16 = 1;
        IOCLR_bit.P0_16 = 1;
 
the output signal on P0_16 would fall after the rising edge of SCLK 
and the signal on P0_16 would not rise after the SPI transfer.  The 
following code worked correctly.

        IOCLR_bit.P0_16 = 1;
        IOCLR_bit.P0_16 = 1;
        S0SPDR_bit.DATA=*ptr;
        ptr++;
        while(!S0SPSR_bit.SPIF);
        IOSET_bit.P0_16 = 1;
        IOSET_bit.P0_16 = 1;
        IOSET_bit.P0_16 = 1;
        IOCLR_bit.P0_16 = 1;

This leads me to believe that the GPIO is very slow. Am I doing 
something wrong or is this really the way it is? 

Thank you,
Bob Davis

Hi Bob,

the maximum SCLK of the SPI Interface is 1/8 of pclk.

If cclk is 60MHz and pclk = cclk you get a maximum SCLK speed of 7.5 MHz.


It seems that your cclk is 14.7 Mhz and pclk is 1/4 of cclk.
Setup your PLL and VPBDIV Register to the right values.

Andreas

--- In lpc2000@yahoogroups.com, "rkdwork" <rdavis@I...> wrote:

> Hi,
> 
> I have been developing software to perform SPI transfers.  I am using 
> a logic analyzer to examine the SCLK, MOSI, MISO and gpio signals.  
> The board I am using is an IAR Kickstart card with a 14.7MHz clock. 
> The first thing that I found was that if I set the SOSPCCR counter 
> field to 8, I got a 460.8KHz SCLK signal and everything looked 
> correct.  If I changed the SOSPCCR counter to 4, I got a 921KHz SCLK 
> signal but the data on MOSI signal shifted so that the correct value 
> was not present on the rising edge of SCLK. CPHA and CPOL are both 
> zero.  At higher SCLK rates I got 9 positive pulses on SCLK instead 
> of 8. Is the maximum usable SCLK limited to somewhere between 460KHz 
> and 921KHz or is something wrong.
> 
> I use a GPIO pin (P0_16) for a CS signal.  I found that if I execute 
> the following code,
> 
>         IOCLR_bit.P0_16 = 1;
>         S0SPDR_bit.DATA=*ptr;
>         ptr++;
>         while(!S0SPSR_bit.SPIF);
>         IOSET_bit.P0_16 = 1;
>         IOCLR_bit.P0_16 = 1;
>  
> the output signal on P0_16 would fall after the rising edge of SCLK 
> and the signal on P0_16 would not rise after the SPI transfer.  The 
> following code worked correctly.
> 
>         IOCLR_bit.P0_16 = 1;
>         IOCLR_bit.P0_16 = 1;
>         S0SPDR_bit.DATA=*ptr;
>         ptr++;
>         while(!S0SPSR_bit.SPIF);
>         IOSET_bit.P0_16 = 1;
>         IOSET_bit.P0_16 = 1;
>         IOSET_bit.P0_16 = 1;
>         IOCLR_bit.P0_16 = 1;
> 
> This leads me to believe that the GPIO is very slow. Am I doing 
> something wrong or is this really the way it is? 
> 
> Thank you,
> Bob Davis

Hi Andreas,

I did as you suggested and the SPI works correctly at much higher 
speeds.  Thank for your help.  This still leaves me with the problem 
of a chip select signal generated by GPIO that is extremely slow and 
if I follow a set too closely behind a clear, I never see the low 
state on the signal line. Am I also doing something wrong with the 
GPIO.  When I step through the code for manipulating the GPIO signal, 
it works as I expect.

Thanks,
Bob Davis

--- In lpc2000@yahoogroups.com, "haack0815" <lpc_arm@s...> wrote:
> Hi Bob,
> 
> the maximum SCLK of the SPI Interface is 1/8 of pclk.
> 
> If cclk is 60MHz and pclk = cclk you get a maximum SCLK speed of 
7.5 MHz.

> 
> 
> It seems that your cclk is 14.7 Mhz and pclk is 1/4 of cclk.
> Setup your PLL and VPBDIV Register to the right values.
> 
> Andreas

Is your VPB clocking set to 1:1?

I find that the GPIO gives me what I would expect (ie correct 
mark/space ratio), though yes it is slow. The maximum I've been able 
to get out of an LPC2106 @ 60MHz is a square wave of between 3 and 
4MHz.


--- In lpc2000@yahoogroups.com, "rkdwork" <rdavis@I...> wrote:
> Hi Andreas,
> 
> I did as you suggested and the SPI works correctly at much higher 
> speeds.  Thank for your help.  This still leaves me with the 
problem 
> of a chip select signal generated by GPIO that is extremely slow 
and 
> if I follow a set too closely behind a clear, I never see the low 
> state on the signal line. Am I also doing something wrong with the 
> GPIO.  When I step through the code for manipulating the GPIO 
signal, 

> it works as I expect.
> 
> Thanks,
> Bob Davis
> 
> --- In lpc2000@yahoogroups.com, "haack0815" <lpc_arm@s...> wrote:
> > Hi Bob,
> > 
> > the maximum SCLK of the SPI Interface is 1/8 of pclk.
> > 
> > If cclk is 60MHz and pclk = cclk you get a maximum SCLK speed of 
> 7.5 MHz.
> > 
> > 
> > It seems that your cclk is 14.7 Mhz and pclk is 1/4 of cclk.
> > Setup your PLL and VPBDIV Register to the right values.
> > 
> > Andreas