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pll configuration problem

pll configuration problem

2004-07-08 by shridharjoshi2000

hi all,
i am trying to boost the PRocessor clock to near full speed by 
setting the PLL registers
but PLL is not locking .
 am i making any mistake in configuring the PLL 
here is my pll setting code 

void SetPLLtoMaxSpeed()
{


  // set PLL multiplier & divisor.
  // values computed from config.h
 REG(SYSCON_PLLCFG)= 0x23;			    //where 
	M=4,P=2, fosc=14.7456MHz,Fcclk=58.98MHz
 REG(SYSCON_PLLFEED) = 0xAA;                      
 REG(SYSCON_PLLFEED) = 0x55; 
   
  // enable PLL
  REG(SYSCON_PLLCON)  = 0x01;
  REG(SYSCON_PLLFEED) = 0xAA;
  REG(SYSCON_PLLFEED) = 0x55;

    // wait for PLL lock
  while (!(REG(SYSCON_PLLSTAT) & 0x0400))           
    continue;

  // enable & connect PLL
  REG(SYSCON_PLLCON) = 0x03;
  REG(SYSCON_PLLFEED)  = 0xAA;
  REG(SYSCON_PLLFEED) = 0x55;

  // setup & enable the MAM
 //MAMTIM = MAMTIM_CYCLES;
 // MAMCR = MAMCR_FULL;

  // set the peripheral bus speed
  // value computed from config.h
  REG(SYSCON_VPBDIV)  = 0x02;                // set the peripheral 
bus clock speed to processor clock

}

thanks

shridhar

Re: pll configuration problem

2004-07-08 by markcrow

For what it's worth, your code is, as I understand it, "by the book" 
as regards programming the PLL.  I haven't got it to work either but 
I AM GETTING A LOCK.  But all my timers, UART baud rates, etc. are 
all out of sync (though I HAVE reprogrammed them to match the new 
clock rate).  I've put the problem on the back burner for now...let's 
hope someone else can help...?????

--- In lpc2000@yahoogroups.com, "shridharjoshi2000" 
<shridharjoshi2000@y...> wrote:
Show quoted textHide quoted text
> hi all,
> i am trying to boost the PRocessor clock to near full speed by 
> setting the PLL registers
> but PLL is not locking .
>  am i making any mistake in configuring the PLL 
> here is my pll setting code 
> 
> void SetPLLtoMaxSpeed()
> {
> 
> 
>   // set PLL multiplier & divisor.
>   // values computed from config.h
>  REG(SYSCON_PLLCFG)= 0x23;			    //where 
> 	M=4,P=2, fosc=14.7456MHz,Fcclk=58.98MHz
>  REG(SYSCON_PLLFEED) = 0xAA;                      
>  REG(SYSCON_PLLFEED) = 0x55; 
>    
>   // enable PLL
>   REG(SYSCON_PLLCON)  = 0x01;
>   REG(SYSCON_PLLFEED) = 0xAA;
>   REG(SYSCON_PLLFEED) = 0x55;
> 
>     // wait for PLL lock
>   while (!(REG(SYSCON_PLLSTAT) & 0x0400))           
>     continue;
> 
>   // enable & connect PLL
>   REG(SYSCON_PLLCON) = 0x03;
>   REG(SYSCON_PLLFEED)  = 0xAA;
>   REG(SYSCON_PLLFEED) = 0x55;
> 
>   // setup & enable the MAM
>  //MAMTIM = MAMTIM_CYCLES;
>  // MAMCR = MAMCR_FULL;
> 
>   // set the peripheral bus speed
>   // value computed from config.h
>   REG(SYSCON_VPBDIV)  = 0x02;                // set the peripheral 
> bus clock speed to processor clock
> 
> }
> 
> thanks
> 
> shridhar

Re: [lpc2000] pll configuration problem

2004-07-08 by Taner Mutlu

try this...

void initCPU(void){
******************************************************************************
  
   MAMCR = 0x00; 
   MAMTIM = 0x03;
   MAMCR = 0x02;
******************************************************************************
  
   VPBDIV = 0x01;
******************************************************************************
  
   PLLCFG = 0x03; 
   PLLCON = 0x01;

   PLLFEED = 0x0AA;
   PLLFEED = 0x055;

   while(!(PLLSTAT & (1<<10))); 

   PLLCON = 0x03; 
   PLLFEED = 0x0AA;
   PLLFEED = 0x055;
}


=====
Taner Mutlu 
Elektronik M\ufffdh.
GLOBAL Bilgisayar ve Kontrol Sistemleri
taner@...


		
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Re: [lpc2000] pll configuration problem

2004-07-08 by Robert Adsett

At 12:52 PM 7/8/04 -0700, you wrote:
>try this...

<snip>

>
>    PLLCFG = 0x03;

That may work but it puts  Fcco out of range which may cause problems.

Robert

" 'Freedom' has no meaning of itself.  There are always restrictions,
be they legal, genetic, or physical.  If you don't believe me, try to
chew a radio signal. "

                         Kelvin Throop, III

Re: [lpc2000] pll configuration problem

2004-07-08 by Robert Adsett

At 07:31 PM 7/8/04 +0000, you wrote:
>hi all,
>i am trying to boost the PRocessor clock to near full speed by
>setting the PLL registers
>but PLL is not locking .
>  am i making any mistake in configuring the PLL
>here is my pll setting code
>
>void SetPLLtoMaxSpeed()
>{
>
>
>   // set PLL multiplier & divisor.
>   // values computed from config.h
>  REG(SYSCON_PLLCFG)= 0x23;                          //where
>         M=4,P=2, fosc=14.7456MHz,Fcclk=58.98MHz
>  REG(SYSCON_PLLFEED) = 0xAA;
>  REG(SYSCON_PLLFEED) = 0x55;

Some basic questions.

There are no interrupts enabled?
What is the definition of REG (I am assuming that SYSCON... etc are simple 
numeric constants)?

There is working code doing this in the newlib-lpc library (it goes so far 
as to take in the oscillator frequency and desired operating frequency and 
use them to calculate the required settings) 
http://www.aeolusdevelopment.com/Articles/download.html

That might be worth comparing to even if you don't use it.

Robert

" 'Freedom' has no meaning of itself.  There are always restrictions,
be they legal, genetic, or physical.  If you don't believe me, try to
chew a radio signal. "

                         Kelvin Throop, III

Re: [lpc2000] pll configuration problem

2004-07-08 by shridhar joshi

hi Robert,
>>uart0 interrupt is enabled in startup.s section of
the code.
and i am setting the Pll configuration in main which
is executed later 

>>the REG defination is as below
#define REG(addr) (*(volatile unsigned long*)(addr))

>>SYS_xxxx ARE ADDRESS for the respective pll
registers

hope to get this thing running 

thanks 

shridhar
--- Robert Adsett
<subscriptions@...> wrote:
> At 07:31 PM 7/8/04 +0000, you wrote:
> >hi all,
> >i am trying to boost the PRocessor clock to near
> full speed by
> >setting the PLL registers
> >but PLL is not locking .
> >  am i making any mistake in configuring the PLL
> >here is my pll setting code
> >
> >void SetPLLtoMaxSpeed()
> >{
> >
> >
> >   // set PLL multiplier & divisor.
> >   // values computed from config.h
> >  REG(SYSCON_PLLCFG)= 0x23;                        
>  //where
> >         M=4,P=2, fosc=14.7456MHz,Fcclk=58.98MHz
> >  REG(SYSCON_PLLFEED) = 0xAA;
> >  REG(SYSCON_PLLFEED) = 0x55;
> 
> Some basic questions.
> 
> There are no interrupts enabled?
> What is the definition of REG (I am assuming that
> SYSCON... etc are simple 
> numeric constants)?
> 
> There is working code doing this in the newlib-lpc
> library (it goes so far 
> as to take in the oscillator frequency and desired
> operating frequency and 
> use them to calculate the required settings) 
>
http://www.aeolusdevelopment.com/Articles/download.html
> 
> That might be worth comparing to even if you don't
> use it.
> 
> Robert
> 
> " 'Freedom' has no meaning of itself.  There are
> always restrictions,
> be they legal, genetic, or physical.  If you don't
> believe me, try to
> chew a radio signal. "
> 
>                          Kelvin Throop, III
> 
> 



		
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Re: [lpc2000] pll configuration problem

2004-07-08 by Robert Adsett

At 02:28 PM 7/8/04 -0700, you wrote:
>hi Robert,
> >>uart0 interrupt is enabled in startup.s section of
>the code.
>and i am setting the Pll configuration in main which
>is executed later

That might be a problem.  The pll_load writes must me successive writes so 
if an interrupt were to occur between writes the update would fail.  I 
think I'd expect your symptoms to be more intermittent though.  nonetheless 
I'd disable interrupts while you are updating the pll (actually I'd disable 
them for the whole routine).  That's a problem but probably not the problem.


> >>the REG defination is as below
>#define REG(addr) (*(volatile unsigned long*)(addr))

I don't believe it's an ANSI compliant lvalue (IE it's not allowed to 
assign to it), but compilers that support it as an lvalue should do the 
logical thing.

Robert

" 'Freedom' has no meaning of itself.  There are always restrictions,
be they legal, genetic, or physical.  If you don't believe me, try to
chew a radio signal. "

                         Kelvin Throop, III

Re: [lpc2000] pll configuration problem

2004-07-08 by Robert Adsett

At 07:31 PM 7/8/04 +0000, you wrote:
>hi all,
>i am trying to boost the PRocessor clock to near full speed by
>setting the PLL registers
>but PLL is not locking .
>  am i making any mistake in configuring the PLL
>here is my pll setting code

<snip>

>     // wait for PLL lock
>   while (!(REG(SYSCON_PLLSTAT) & 0x0400))
>     continue;

Another basic question.  How do you know you are failing here and not 
somewhere else?

Robert

" 'Freedom' has no meaning of itself.  There are always restrictions,
be they legal, genetic, or physical.  If you don't believe me, try to
chew a radio signal. "

                         Kelvin Throop, III

Re: pll configuration problem

2004-07-09 by johnnorgaard2003

--- In lpc2000@yahoogroups.com, Robert Adsett <subscriptions@a...> 
wrote:
> At 02:28 PM 7/8/04 -0700, you wrote:
> >hi Robert,
> > >>uart0 interrupt is enabled in startup.s section of
> >the code.
> >and i am setting the Pll configuration in main which
> >is executed later
> 
> That might be a problem.  The pll_load writes must me successive 
writes so 
> if an interrupt were to occur between writes the update would 
fail.  I 
> think I'd expect your symptoms to be more intermittent though.  
nonetheless 
> I'd disable interrupts while you are updating the pll (actually I'd 
disable 
> them for the whole routine).  That's a problem but probably not the 
problem.
> 
> 
> > >>the REG defination is as below
> >#define REG(addr) (*(volatile unsigned long*)(addr))
> 
> I don't believe it's an ANSI compliant lvalue (IE it's not allowed 
to 
> assign to it), but compilers that support it as an lvalue should do 
the 
> logical thing.
> 
> Robert
> 
> " 'Freedom' has no meaning of itself.  There are always 
restrictions,
> be they legal, genetic, or physical.  If you don't believe me, try 
to
> chew a radio signal. "
> 
>                          Kelvin Throop, III

Hi 

Maybe the problem is the define of REG. It should not always be long.

/* Memory Accelerator Module (MAM) */
#define MAMCR (*(volatile unsigned char *)0xe01fc000)
#define MAMTIM (*(volatile unsigned char *)0xe01fc004)
#define MEMMAP (*(volatile unsigned char *)0xe01fc040)


/* Phase Locked Loop (PLL) */
#define PLLCON 	(*(volatile unsigned char *)0xe01fc080)
#define PLLCFG 	(*(volatile unsigned char *)0xe01fc084)
#define PLLSTAT (*(volatile unsigned short *)0xe01fc088)
#define PLLFEED (*(volatile unsigned char *)0xe01fc08c)
#define PCON 	(*(volatile unsigned char *)0xe01fc0c0)
#define PCONP 	(*(volatile unsigned long *)0xe01fc0c4)

John

SV: [lpc2000] Re: pll configuration problem

2004-07-09 by Lasse Madsen

Hi John

How and why can you make a char pointer to a long address ? 

#define MAMCR (*(volatile unsigned char *)0xe01fc000)

Will writing MAMCR=0x01; make the "pointer" write: 0xe01fc001  ?

Best regards
lasse madsen

-----Oprindelig meddelelse-----
Fra: johnnorgaard2003 [mailto:john_2005@...]
Sendt: 9. juli 2004 11:15
Til: lpc2000@yahoogroups.com
Emne: [lpc2000] Re: pll configuration problem


--- In lpc2000@yahoogroups.com, Robert Adsett <subscriptions@a...> 
wrote:
> At 02:28 PM 7/8/04 -0700, you wrote:
> >hi Robert,
> > >>uart0 interrupt is enabled in startup.s section of
> >the code.
> >and i am setting the Pll configuration in main which
> >is executed later
> 
> That might be a problem.  The pll_load writes must me successive 
writes so 
> if an interrupt were to occur between writes the update would 
fail.  I 
> think I'd expect your symptoms to be more intermittent though.  
nonetheless 
> I'd disable interrupts while you are updating the pll (actually I'd 
disable 
> them for the whole routine).  That's a problem but probably not the 
problem.
> 
> 
> > >>the REG defination is as below
> >#define REG(addr) (*(volatile unsigned long*)(addr))
> 
> I don't believe it's an ANSI compliant lvalue (IE it's not allowed 
to 
> assign to it), but compilers that support it as an lvalue should do 
the 
> logical thing.
> 
> Robert
> 
> " 'Freedom' has no meaning of itself.  There are always 
restrictions,
> be they legal, genetic, or physical.  If you don't believe me, try 
to
> chew a radio signal. "
> 
>                          Kelvin Throop, III

Hi 

Maybe the problem is the define of REG. It should not always be long.

/* Memory Accelerator Module (MAM) */
#define MAMCR (*(volatile unsigned char *)0xe01fc000)
#define MAMTIM (*(volatile unsigned char *)0xe01fc004)
#define MEMMAP (*(volatile unsigned char *)0xe01fc040)


/* Phase Locked Loop (PLL) */
#define PLLCON 	(*(volatile unsigned char *)0xe01fc080)
#define PLLCFG 	(*(volatile unsigned char *)0xe01fc084)
#define PLLSTAT (*(volatile unsigned short *)0xe01fc088)
#define PLLFEED (*(volatile unsigned char *)0xe01fc08c)
#define PCON 	(*(volatile unsigned char *)0xe01fc0c0)
#define PCONP 	(*(volatile unsigned long *)0xe01fc0c4)

John





 
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SV: [lpc2000] Re: pll configuration problem

2004-07-09 by johnnorgaard2003

--- In lpc2000@yahoogroups.com, "Lasse Madsen" <lm@h...> wrote:
> Hi John
> 
> How and why can you make a char pointer to a long address ? 
> 
> #define MAMCR (*(volatile unsigned char *)0xe01fc000)
> 
> Will writing MAMCR=0x01; make the "pointer" write: 0xe01fc001  ?
> 
> Best regards
> lasse madsen
> 
> -----Oprindelig meddelelse-----
> Fra: johnnorgaard2003 [mailto:john_2005@c...]
> Sendt: 9. juli 2004 11:15
> Til: lpc2000@yahoogroups.com
> Emne: [lpc2000] Re: pll configuration problem
> 
> 
> --- In lpc2000@yahoogroups.com, Robert Adsett <subscriptions@a...> 
> wrote:
> > At 02:28 PM 7/8/04 -0700, you wrote:
> > >hi Robert,
> > > >>uart0 interrupt is enabled in startup.s section of
> > >the code.
> > >and i am setting the Pll configuration in main which
> > >is executed later
> > 
> > That might be a problem.  The pll_load writes must me successive 
> writes so 
> > if an interrupt were to occur between writes the update would 
> fail.  I 
> > think I'd expect your symptoms to be more intermittent though.  
> nonetheless 
> > I'd disable interrupts while you are updating the pll (actually 
I'd 
> disable 
> > them for the whole routine).  That's a problem but probably not 
the 
> problem.
> > 
> > 
> > > >>the REG defination is as below
> > >#define REG(addr) (*(volatile unsigned long*)(addr))
> > 
> > I don't believe it's an ANSI compliant lvalue (IE it's not 
allowed 
> to 
> > assign to it), but compilers that support it as an lvalue should 
do 
> the 
> > logical thing.
> > 
> > Robert
> > 
> > " 'Freedom' has no meaning of itself.  There are always 
> restrictions,
> > be they legal, genetic, or physical.  If you don't believe me, 
try 
> to
> > chew a radio signal. "
> > 
> >                          Kelvin Throop, III
> 
> Hi 
> 
> Maybe the problem is the define of REG. It should not always be 
long.
> 
> /* Memory Accelerator Module (MAM) */
> #define MAMCR (*(volatile unsigned char *)0xe01fc000)
> #define MAMTIM (*(volatile unsigned char *)0xe01fc004)
> #define MEMMAP (*(volatile unsigned char *)0xe01fc040)
> 
> 
> /* Phase Locked Loop (PLL) */
> #define PLLCON 	(*(volatile unsigned char *)0xe01fc080)
> #define PLLCFG 	(*(volatile unsigned char *)0xe01fc084)
> #define PLLSTAT (*(volatile unsigned short *)0xe01fc088)
> #define PLLFEED (*(volatile unsigned char *)0xe01fc08c)
> #define PCON 	(*(volatile unsigned char *)0xe01fc0c0)
> #define PCONP 	(*(volatile unsigned long *)0xe01fc0c4)
> 
> John
> 
> 
> 
> 
> 
>  
> Yahoo! Groups Links


Hej Lasse

No all the pointers are long, but what the point to is char, short 
int or long.

See keil register defines.
http://www.keil.com/dd/docs/arm/philips/lpc210x.h

Some register bit of LPC210x is unused and you should write 00.

Best regards

John

Re: [lpc2000] Re: pll configuration problem

2004-07-09 by Robert Adsett

At 09:14 AM 7/9/04 +0000, you wrote:
>Maybe the problem is the define of REG. It should not always be long.
>
>/* Memory Accelerator Module (MAM) */
>#define MAMCR (*(volatile unsigned char *)0xe01fc000)

Yes some of the registers are only 8 bits wide but the documentation 
indicates they are accessed as words.  It's useful to define them as char 
for documentation purposes but it shouldn't effect the result.

Robert

" 'Freedom' has no meaning of itself.  There are always restrictions,
be they legal, genetic, or physical.  If you don't believe me, try to
chew a radio signal. "

                         Kelvin Throop, III

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