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2005-05-08 by soren_t_hansen
I'm making an application on a LPC2132, that must performe a number of DSP operations. To find out how many operations I can perform, I need to know how many clock cycles it takes the LPC2132 to performe a 16 bit times 16 bit = 32 bit multiplication? Best Regards Søren Hansen
2005-05-08 by Karl Olsen
--- In lpc2000@yahoogroups.com, "soren_t_hansen" < soren_t_hansen@y...> wrote: > I'm making an application on a LPC2132, that must performe a number > of DSP operations. To find out how many operations I can perform, I > need to know how many clock cycles it takes the LPC2132 to performe > a 16 bit times 16 bit = 32 bit multiplication? The ARM7TDMI has a 8x32 hardware multiplier (the "M" in TDMI), and the number of cycles the MUL instruction takes depends on the multiplier operand: 2 cycles if bit 8-31 are all zeroes or all ones 3 cycles if bit 16-31 are all zeroes or all ones 4 cycles if bit 24-31 are all zeroes or all ones 5 cycles in all other cases So in your case, a MUL takes 2 or 3 cycles. Karl Olsen
2005-05-08 by Karl Olsen
--- In lpc2000@yahoogroups.com, "soren_t_hansen" < soren_t_hansen@y...> wrote: > I'm making an application on a LPC2132, that must performe a number > of DSP operations. To find out how many operations I can perform, I > need to know how many clock cycles it takes the LPC2132 to performe > a 16 bit times 16 bit = 32 bit multiplication? The ARM7TDMI has a 8x32 hardware multiplier (the "M" in TDMI), and the number of cycles the MUL instruction takes depends on the multiplier operand: 2 cycles if bit 8-31 are all zeroes or all ones 3 cycles if bit 16-31 are all zeroes or all ones 4 cycles if bit 24-31 are all zeroes or all ones 5 cycles in all other cases So in your case, a MUL takes 2 or 3 cycles. Karl Olsen
2005-05-09 by James Dabbs
> I'm making an application on a LPC2132, that must performe a > number of DSP operations. To find out how many operations I > can perform, I need to know how many clock cycles it takes > the LPC2132 to performe a 16 bit times 16 bit = 32 bit multiplication? I believe it's 2-5 cycles to execute the MUL instruction. Compared to dedicated DSP's, I've found the bigger limitation to be ARM's lack of circular buffer management. In a 4-pole IIR filter, I saw most of the CPU BW spent managing pointers and ldr/str'ing rather than doing the actual math.
2005-05-10 by brendanmurphy37
I'd agree: speed of the multiply is only part of the issue. We've been implementing DSP-type code on 32-bit RISC for a few years now (and on the LPC2000 series since it came out). A few pointers: 1. Generally, for core DSP-type functions, you're looking at a factor of about 10:1 over the speed of a pure DSP for most filter operations. The bulk of this is taken up with buffer management: it's the lack of circular buffers with single cycle updating of pointers that's the real killer. 2. Having said that, there's a lot you can do with the available speed: we run a V.22bis modem on the part with plenty of CPU left over. This uses a significant amount of both FIR and IIR filtering. 3. Only real way to get a figure for the speed of a multiply is to do some simple benchmarking, making sure you use real data (i.e. not zero times zero). Try putting together an inner-core of multiply and shift operations, and putting it in a wrapper that's called 100k times, and timing how long the whole lot takes. 4. Optimisation settings on the compiler are ***critical***. This is common to practically all RISC architectures and all compilers for them. The good news is that the compilers are very good at optimising. We use the GNU on ARM7 and IAR for some other platforms. From memory we use the next to highest level of optimisation for the GNU (the highest tends to bloat the code size too much): contact me directly if you want more details. Note: we have had problems in the past with IAR at high optimisation levels with it producing bad (i.e. wrong) code. The best approach is to look at the assembler output from the compiler for the critical sections of code, and chose the optimisation setting that gives the best results. The bottom line is that we've found no need to hand-code in assembler. 5. There are a few tricks you can do with pointers to speed the implementation of filters. Can't give any details I'm afraid. 6. One thing I would say is that for very small filters (e.g. the 4-tap IIR mentioned below), we've found it more efficient to move the data through the filter, rather than use pointers, as in: reg[3] = reg[2]; reg[2] = reg[1]; reg[1] = reg[0]; reg[0] = new; Hope this is of some help. BTW: I'd be curious to hear what other people are doing in this area (i.e. DSP on RISC). Regards Brendan Murphy --- In lpc2000@yahoogroups.com, "James Dabbs" <jdabbs@t...> wrote: > > I'm making an application on a LPC2132, that must performe a > > number of DSP operations. To find out how many operations I > > can perform, I need to know how many clock cycles it takes > > the LPC2132 to performe a 16 bit times 16 bit = 32 bit multiplication? > > I believe it's 2-5 cycles to execute the MUL instruction. > > Compared to dedicated DSP's, I've found the bigger limitation to be > ARM's lack of circular buffer management. In a 4-pole IIR filter, I saw > most of the CPU BW spent managing pointers and ldr/str'ing rather than > doing the actual math.
2005-05-28 by James Dabbs
> 6. One thing I would say is that for very small filters (e.g. > the 4-tap IIR mentioned below), we've found it more efficient to move the > data through the filter, rather than use pointers, as in: > > reg[3] = reg[2]; > reg[2] = reg[1]; > reg[1] = reg[0]; > reg[0] = new; > > Hope this is of some help. This is exactly what I did. I think you come out ahead even with more taps, especially if you use inline asm and LDM/STM to do the actual move. Also, it doesn't bridge the performance gap, but ARM is a 32-bit fixed point processor, compared to most fixed point DSP's I know about which are all 16- or 24-bit. The extra bits are nice for IIR and other applications where dynamic range can make a real difference.
2005-06-12 by sudip nag
Dear All, I would like to generate 60 MHz to 100 MHz clock, in controlled step of 1 MHz, with 50% duty cycle using LPC2138. Any suggestion how to generate the same. Match functionality is inappropriate for generating such high frequency. Sudip --------------------------------- Free antispam, antivirus and 1GB to save all your messages Only in Yahoo! Mail: http://in.mail.yahoo.com [Non-text portions of this message have been removed]
2005-06-12 by Leon Heller
----- Original Message -----
From: "sudip nag" <sudipnag1@...> To: <lpc2000@yahoogroups.com> Sent: Sunday, June 12, 2005 7:16 AM Subject: [lpc2000] 100 MHz clock using LPC2138 > > > Dear All, > > I would like to generate 60 MHz to 100 MHz clock, in controlled step of 1 > MHz, with 50% duty cycle using LPC2138. Any suggestion how to generate the > same. Match functionality is inappropriate for generating such high > frequency. A PLL sythesiser is the best way, with a programmable divider controlled by the '2138. You could use a synthesiser chip like those from Nat. Semi. and a VCO, or make your own synthesiser. Leon -- Leon Heller, G1HSM leon.heller@... http://www.geocities.com/leon_heller --- [This E-mail has been scanned for viruses but it is your responsibility to maintain up to date anti virus software on the device that you are currently using to read this email. ]
2005-06-12 by weverest3
--- In lpc2000@yahoogroups.com, sudip nag <sudipnag1@y...> wrote: > I would like to generate 60 MHz to 100 MHz clock, in controlled step of 1 MHz, with 50% duty cycle using LPC2138. Any suggestion how to generate the same. Match functionality is inappropriate for generating such high frequency. The Si4112 (derivative of Si4133) from www.silabs.com has an output from 62 MHz to 1 GHz (and the part will work lower). They are available from Digikey. -Wallie
2005-06-12 by sudip nag
My requirement is basically to transmit data from one microcontroller (LPC2138) to the other at 100MHz. Thus the clock generated must synchronize the data. Si4112 has IF out relying upon its separate crystal. This may cause data transition mismatch with driving clock. So its preferable to generate clock from LPC2138. Please suggest any outcome. Sudip weverest3 <weverest@...> wrote: --- In lpc2000@yahoogroups.com, sudip nag <sudipnag1@y...> wrote: > I would like to generate 60 MHz to 100 MHz clock, in controlled step of 1 MHz, with 50% duty cycle using LPC2138. Any suggestion how to generate the same. Match functionality is inappropriate for generating such high frequency. The Si4112 (derivative of Si4133) from www.silabs.com has an output from 62 MHz to 1 GHz (and the part will work lower). They are available from Digikey. -Wallie --------------------------------- Yahoo! Groups Links To visit your group on the web, go to: http://groups.yahoo.com/group/lpc2000/ To unsubscribe from this group, send an email to: lpc2000-unsubscribe@yahoogroups.com Your use of Yahoo! Groups is subject to the Yahoo! Terms of Service. --------------------------------- Free antispam, antivirus and 1GB to save all your messages Only in Yahoo! Mail: http://in.mail.yahoo.com [Non-text portions of this message have been removed]
2005-06-12 by Robert Adsett
At 05:25 PM 6/12/05 +0100, sudip nag wrote: >My requirement is basically to transmit data from one microcontroller >(LPC2138) to the other at 100MHz. Thus the clock generated must >synchronize the data. Si4112 has IF out relying upon its separate crystal. >This may cause data transition mismatch with driving clock. So its >preferable to generate clock from LPC2138. Please suggest any outcome. If you mean the LPC is to generate and clock out data at 100MHz it's not going to happen. The LPC is only a 60MHz device. BTW, where are you getting the 100MHz requirement? I took a quick look at the Si4112 datasheet out of curiosity and sclk is restricted to a min of 40nS. Robert " 'Freedom' has no meaning of itself. There are always restrictions, be they legal, genetic, or physical. If you don't believe me, try to chew a radio signal. " -- Kelvin Throop, III http://www.aeolusdevelopment.com/
2005-06-12 by Micron Engineering
sudip nag ha scritto: >My requirement is basically to transmit data from one microcontroller (LPC2138) to the other at 100MHz. Thus the clock generated must synchronize the data. Si4112 has IF out relying upon its separate crystal. This may cause data transition mismatch with driving clock. So its preferable to generate clock from LPC2138. Please suggest any outcome. > > > LPC2138 may have a clock lower then 60MHz so it is not possible to generate directly from LPC2138 100MHz clock. Also if you need to transfer data from a LPC2138 to a different mcu you may not do it at 100MHz. I think that also using assembler you may transmit to a fraction of 60MHz may be burst data at 10MHz if your mcu hasn't to do anything else. >Sudip > >weverest3 <weverest@...> wrote: >--- In lpc2000@yahoogroups.com, sudip nag <sudipnag1@y...> wrote: > > >>I would like to generate 60 MHz to 100 MHz clock, in controlled step >> >> >of 1 MHz, with 50% duty cycle using LPC2138. Any suggestion how to >generate the same. Match functionality is inappropriate for generating >such high frequency. > >The Si4112 (derivative of Si4133) from www.silabs.com has an output >from 62 MHz to 1 GHz (and the part will work lower). They are >available from Digikey. > >-Wallie > > > > >--------------------------------- >Yahoo! Groups Links > > To visit your group on the web, go to: >http://groups.yahoo.com/group/lpc2000/ > > To unsubscribe from this group, send an email to: >lpc2000-unsubscribe@yahoogroups.com > > Your use of Yahoo! Groups is subject to the Yahoo! Terms of Service. > > > >--------------------------------- > Free antispam, antivirus and 1GB to save all your messages > Only in Yahoo! Mail: http://in.mail.yahoo.com > >[Non-text portions of this message have been removed] > > > > >Yahoo! Groups Links > > > > > > > > > > ---------- No virus found in this outgoing message. Checked by AVG Anti-Virus. Version: 7.0.323 / Virus Database: 267.6.7 - Release Date: 10/06/2005 [Non-text portions of this message have been removed]
2005-06-14 by Bruce Paterson
> sudip nag ha scritto:
>> My requirement is basically to transmit data from one
>> microcontroller (LPC2138) to the other at 100MHz. Thus the clock
>> generated must synchronize the data. Si4112 has IF out relying upon
>> its separate crystal. This may cause data transition mismatch with
>> driving clock. So its preferable to generate clock from LPC2138.
>> Please suggest any outcome.
Without knowing your exact requirements, or whether a common multiple
can be found which lets you do all you need, why not run both chips from
the same crystal clock circuit ?
I'm assuming here you mean the data carrier is 100MHz, not the actual
data rate (which of course would not be possible from a slower LPC
unless you have external FIFO's or something).
--
Cheers,
Bruce
-------------------------------------------------------------------
/\\\/\\\/\\\ / / Bruce Paterson
/ \\\ \\\ \\\ / / Senior Design Engineer
/ /\\\/\\\/\\\/ / 8 Anzed Court, Mulgrave, Vic, 3170
/ / \\\ \\\ \\\ / PO Box 4112, Mulgrave, Vic, 3170, Australia
/ / \\\/\\\ \\\/ Ph: +61 3 8561 4232 Fax: +61 3 9560 9055
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-------------------------------------------------------------------2005-06-14 by sudip nag
Hi,
My requirement is to interface Gigabit ethernet transceiver (>=500Mbps or >=64 mega bytes per second). The data feeding technique is to supply 8 bit parallel data along with a clock that must exceed 64 MHz (64 mega bytes per second). Here I must synchronize each cycle of clock with data byte. So I need to generate such high clock frequency.
Please suggest.
Sudip
Bruce Paterson <bruce@...> wrote:
Without knowing your exact requirements, or whether a common multiple
can be found which lets you do all you need, why not run both chips from
the same crystal clock circuit ?
I'm assuming here you mean the data carrier is 100MHz, not the actual
data rate (which of course would not be possible from a slower LPC
unless you have external FIFO's or something).
--
Cheers,
Bruce
-------------------------------------------------------------------
/\\\/\\\/\\\ / / Bruce Paterson
/ \\\ \\\ \\\ / / Senior Design Engineer
/ /\\\/\\\/\\\/ / 8 Anzed Court, Mulgrave, Vic, 3170
/ / \\\ \\\ \\\ / PO Box 4112, Mulgrave, Vic, 3170, Australia
/ / \\\/\\\ \\\/ Ph: +61 3 8561 4232 Fax: +61 3 9560 9055
Tele-IP Ltd. Email: bruce@... Icq: #32015991
WWW: http://www.tele-ip.com VK3TJN
-------------------------------------------------------------------
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[Non-text portions of this message have been removed]2005-06-14 by Micron Engineering
sudip nag ha scritto: >Hi, >My requirement is to interface Gigabit ethernet transceiver (>=500Mbps or >=64 mega bytes per second). The data feeding technique is to supply 8 bit parallel data along with a clock that must exceed 64 MHz (64 mega bytes per second). Here I must synchronize each cycle of clock with data byte. So I need to generate such high clock frequency. >Please suggest. > > I think you have to study better your problem. Actually you may transmit and receive data burst at gigabit frequency WITHOUT to write data to the transceiver at gigabit frequency; to do this also just for some data burst you will need mcu with a clock frequency 10 or moretimes higher then 64Mb. You have to choose a chip similar to CS8900 (that works at 10Mb) and then write the chip data buffers at lower frequency (you have to check bus access timings dictated by the transceiver) so your transceiver will send and receive bursts of 1 Gb data and your mcu may rd/wr at its nominal bus frequency. This means that you will not e able to send continuous data streams at 1Gb but this is normally accepted, the only thing to measure is the response time from one packet reception to packet handling and you have to manage the transceiver data buffers (normally queue buffers) with one or more memory buffers/queue to have a longer data burst handled at 1Gb. > >Sudip > >Bruce Paterson <bruce@...> wrote: > >Without knowing your exact requirements, or whether a common multiple >can be found which lets you do all you need, why not run both chips from >the same crystal clock circuit ? >I'm assuming here you mean the data carrier is 100MHz, not the actual >data rate (which of course would not be possible from a slower LPC >unless you have external FIFO's or something). > > -- No virus found in this outgoing message. Checked by AVG Anti-Virus. Version: 7.0.323 / Virus Database: 267.6.9 - Release Date: 11/06/2005
2005-06-14 by Robert Adsett
At 01:00 PM 6/14/05 +0100, sudip nag wrote: >Hi, >My requirement is to interface Gigabit ethernet transceiver (>=500Mbps >or >=64 mega bytes per second). The data feeding technique is to supply 8 >bit parallel data along with a clock that must exceed 64 MHz (64 mega >bytes per second). Here I must synchronize each cycle of clock with data >byte. So I need to generate such high clock frequency. >Please suggest. What chip are you using that requires that kind of minimum? It might be possible to burst at this rate with some sort of FIFO setup but there is no way an LPC210xx is going to approach this speed. Robert " 'Freedom' has no meaning of itself. There are always restrictions, be they legal, genetic, or physical. If you don't believe me, try to chew a radio signal. " -- Kelvin Throop, III http://www.aeolusdevelopment.com/
2005-06-15 by sudip nag
I am using TLK1201 from TI for gigabit ethernet interface. Robert Adsett <subscriptions@...> wrote: At 01:00 PM 6/14/05 +0100, sudip nag wrote: >Hi, >My requirement is to interface Gigabit ethernet transceiver (>=500Mbps >or >=64 mega bytes per second). The data feeding technique is to supply 8 >bit parallel data along with a clock that must exceed 64 MHz (64 mega >bytes per second). Here I must synchronize each cycle of clock with data >byte. So I need to generate such high clock frequency. >Please suggest. What chip are you using that requires that kind of minimum? It might be possible to burst at this rate with some sort of FIFO setup but there is no way an LPC210xx is going to approach this speed. Robert --------------------------------- How much free photo storage do you get? Store your friends n family photos for FREE with Yahoo! Photos. http://in.photos.yahoo.com [Non-text portions of this message have been removed]
2005-06-15 by Robert Adsett
Text rearranged for clarity At 08:30 AM 6/15/05 +0100, sudip nag wrote: >Robert Adsett <subscriptions@...> wrote: >At 01:00 PM 6/14/05 +0100, sudip nag wrote: > >Hi, > >My requirement is to interface Gigabit ethernet transceiver (>=500Mbps > >or >=64 mega bytes per second). The data feeding technique is to supply 8 > >bit parallel data along with a clock that must exceed 64 MHz (64 mega > >bytes per second). Here I must synchronize each cycle of clock with data > >byte. So I need to generate such high clock frequency. > >Please suggest. > >What chip are you using that requires that kind of minimum? -- >I am using TLK1201 from TI for gigabit ethernet interface. -- I think I'm beginning to understand. I'm stepping into a field I'm not familiar with but from the looks of things that is a serializer/deserializer only. It is meant to be part of a multi-chip set with another chip providing the MAC and protocol functions. Trying to hookup a lpc2138 directly to this strikes me as an exercise in futility. It might be possible to add FIFO between the two but that's a fair amount of work for little return. Why not hookup a 10base-t module? It would probably still be faster than you can manage. Robert " 'Freedom' has no meaning of itself. There are always restrictions, be they legal, genetic, or physical. If you don't believe me, try to chew a radio signal. " -- Kelvin Throop, III http://www.aeolusdevelopment.com/
2005-06-15 by gregdeuerling
--- In lpc2000@yahoogroups.com, Robert Adsett <subscriptions@a...> wrote: > Text rearranged for clarity > > At 08:30 AM 6/15/05 +0100, sudip nag wrote: > >Robert Adsett <subscriptions@a...> wrote: > >At 01:00 PM 6/14/05 +0100, sudip nag wrote: > > >Hi, > > >My requirement is to interface Gigabit ethernet transceiver > > >=500Mbps or >=64 mega bytes per second). The data feeding > > >technique is to supply 8 bit parallel data along with a > > >clock that must exceed 64 MHz(64 mega bytes per second). > > >Here I must synchronize each cycle of clock with data > > >byte. So I need to generate such high clock frequency. > > >Please suggest. > > > >What chip are you using that requires that kind of minimum? > > >I am using TLK1201 from TI for gigabit ethernet interface. > > -- > > I think I'm beginning to understand. I'm stepping into a field > I'm not familiar with but from the looks of things that is a > serializer/deserializer only. It is meant to be part of a > multi-chip set with another chip providing the MAC and > protocol functions. > Trying to hookup a lpc2138 directly to this strikes me as an > exercise in futility. It might be possible to add FIFO between > the two but that's a fair amount of work for little return. > Why not hookup a 10base-t module? It would probably still be > faster than you can manage. > Robert Yup, Roberts right. Your going to need a fifo, or better yet, a small FPGA.
2005-06-15 by Lee, Ron
Sudip. Robert and Greg are right. Do you really need a 1 gigabit interface? How familiar are you with Ethernet? The LPC21xx is not really designed for Ethernet applications. Using a 10bit Ethernet controller designed for a microcontroller is more appropriate for the LPC22xx family. The TLK1201 is a 10 bit serializer / deserializer ONLY. The TLK1201 requires 10 bit data clocked at 125MHz. You will need a high performance FPGA to convert an 8 bit byte to a 10 bit symbol just to think about using the TLK1201. I use to work as a hardware engineer for a telecom company. There are better solutions for communicating at 1gbps speeds. Ron ________________________________
From: lpc2000@yahoogroups.com [mailto:lpc2000@yahoogroups.com] On Behalf Of gregdeuerling Sent: Wednesday, June 15, 2005 6:27 AM To: lpc2000@yahoogroups.com Subject: [lpc2000] Re: 100 MHz clock using LPC2138 * --- In lpc2000@yahoogroups.com, Robert Adsett <subscriptions@a...> wrote: > Text rearranged for clarity > > At 08:30 AM 6/15/05 +0100, sudip nag wrote: > >Robert Adsett <subscriptions@a...> wrote: > >At 01:00 PM 6/14/05 +0100, sudip nag wrote: > > >Hi, > > >My requirement is to interface Gigabit ethernet transceiver > > >=500Mbps or >=64 mega bytes per second). The data feeding > > >technique is to supply 8 bit parallel data along with a > > >clock that must exceed 64 MHz(64 mega bytes per second). > > >Here I must synchronize each cycle of clock with data > > >byte. So I need to generate such high clock frequency. > > >Please suggest. > > > >What chip are you using that requires that kind of minimum? > > >I am using TLK1201 from TI for gigabit ethernet interface. > > -- > > I think I'm beginning to understand. I'm stepping into a field > I'm not familiar with but from the looks of things that is a > serializer/deserializer only. It is meant to be part of a > multi-chip set with another chip providing the MAC and > protocol functions. > Trying to hookup a lpc2138 directly to this strikes me as an > exercise in futility. It might be possible to add FIFO between > the two but that's a fair amount of work for little return. > Why not hookup a 10base-t module? It would probably still be > faster than you can manage. > Robert Yup, Roberts right. Your going to need a fifo, or better yet, a small FPGA. [Non-text portions of this message have been removed]
2005-07-08 by sudip nag
Hi Everyone, I am searching for ethernet transformer (E2023 or TS2023) in order to interface CS8900A-CQ3 (3.3V version) with LPC, but unable to find the same. Enyone with idea about the outlet for procurement. Digikey is not supplying the same. Sudip --------------------------------- Free antispam, antivirus and 1GB to save all your messages Only in Yahoo! Mail: http://in.mail.yahoo.com [Non-text portions of this message have been removed]
2005-07-08 by Bill Knight
I ordered some online from Arrow about a year ago. http://www.arrownac.com -Bill Knight R O SoftWare & http://www.theARMPatch.com
On Fri, 8 Jul 2005 05:32:38 +0100 (BST), sudip nag wrote: >Hi Everyone, >I am searching for ethernet transformer (E2023 or TS2023) in order to interface CS8900A-CQ3 (3.3V version) with LPC, but unable to find the same. Enyone with idea about the outlet for procurement. Digikey is not supplying the same. >Sudip
2005-07-12 by sudip nag
Can anyone help me to find how to enable EINT0 in FIQ or IRQ mode using CrossStudio1.4 IDE (LPC2138). I like to connect a switch to this pin and trigger while necessary. Sudip --------------------------------- How much free photo storage do you get? Store your friends n family photos for FREE with Yahoo! Photos. http://in.photos.yahoo.com [Non-text portions of this message have been removed]