Lpc2000

I'm working on designing a new project where we need to process 9600bps 
packets (similar to G3RUH format), we'd like to use the LPC2106 which 
ought to be fast enough. But I'm having trouble coming up with a 
suitable  ADC. It needs to sample at 48khz, 10 bits are fine, 2 
channels. It needs to be consistent (no jitter).

I could use a SPI ADC with the ARM as the SPI master, but I'm afraid 
that other interrupts in the system will effect the sample accuracy (it 
will also be doing some serial communications and have some timers 
running) and introduce jitter into sample rate.

Ideally the ADC would be a SPI master with its own reference clock, 
feeding the samples to the ARM with some indication (high bit 
set/clear?) of which channel the data came from. There are some AKM 
ADCs/codecs that might work, but their left/right clock would somehow 
need to be associated with the data -- hard to do if you have a delay in 
getting to the interrupt to process the data and L/R has already 
switched to the other channel.

Any thoughts?

Thanks,

Brian

-- 
-----------------------------------------------------
Brian C. Lane (W7BCL)                      Programmer
www.shinemicro.com   RF, DSP & Microcontroller Design

Brian C. Lane wrote:
> I'm working on designing a new project where we need to process 9600bps 
> packets (similar to G3RUH format), we'd like to use the LPC2106 which 
> ought to be fast enough. But I'm having trouble coming up with a 
> suitable  ADC. It needs to sample at 48khz, 10 bits are fine, 2 
> channels. It needs to be consistent (no jitter).
> 
> I could use a SPI ADC with the ARM as the SPI master, but I'm afraid 
> that other interrupts in the system will effect the sample accuracy (it 
> will also be doing some serial communications and have some timers 
> running) and introduce jitter into sample rate.

Can you not do the SPI sample activity from a timer interrupt handler, 
assigned to a nice high priority interrupt in that lovely vectored 
interrupt controller, so other timers and serial comms wait for it to 
complete, or will that make it impossible to service the other 
interrupts in time due to the SPI delays?

You could also rig up a system where the timer triggers the SPI action 
to request the sample, with the SPI device interrupting upon completion, 
the handler of which then triggers the SPI write to request the sample 
to be read back, then the next time the handler is called it triggers 
the SPI read of the sample... thus letting other things run. But still 
having the initial timer, and subsequent SPI, interrupts at a high priority.

ABS

On Mon, 02 Feb 2004 08:34:01 -0800, Brian C. Lane wrote:

I'm working on designing a new project where we need to process 9600bps 
packets (similar to G3RUH format), we'd like to use the LPC2106 which 
ought to be fast enough. But I'm having trouble coming up with a 
suitable  ADC. It needs to sample at 48khz, 10 bits are fine, 2 
channels. It needs to be consistent (no jitter).

I could use a SPI ADC with the ARM as the SPI master, but I'm afraid 
that other interrupts in the system will effect the sample accuracy (it 
will also be doing some serial communications and have some timers 
running) and introduce jitter into sample rate.

Ideally the ADC would be a SPI master with its own reference clock, 
feeding the samples to the ARM with some indication (high bit 
set/clear?) of which channel the data came from. There are some AKM 
ADCs/codecs that might work, but their left/right clock would somehow 
need to be associated with the data -- hard to do if you have a delay in 
getting to the interrupt to process the data and L/R has already 
switched to the other channel.

=======================================================================
Brian
  This should be available soon.
-Bill Knight
R O SoftWare

ARM-based Microcontroller LPC2114/2124/2212/2214

A/D CONVERTER FEATURES
" 10 bit successive approximation analog to digital converter.
" Input multiplexing among 4 pins (LPC2114/2124) or 8 pins (LPC2212/2214)
" Power down mode
" Measurement range 0 to 3 V
" 10 bit conversion time >= 2.44 uS
" Burst conversion mode for single or multiple inputs
" Optional conversion on transition on input pin or Timer Match signal

Bill Knight wrote:


> Brian
>   This should be available soon.
> -Bill Knight
> R O SoftWare
> 
> ARM-based Microcontroller LPC2114/2124/2212/2214
> 
> A/D CONVERTER FEATURES
> " 10 bit successive approximation analog to digital converter.
> " Input multiplexing among 4 pins (LPC2114/2124) or 8 pins (LPC2212/2214)
> " Power down mode
> " Measurement range 0 to 3 V
> " 10 bit conversion time >= 2.44 uS
> " Burst conversion mode for single or multiple inputs
> " Optional conversion on transition on input pin or Timer Match signal

Yeah, I know. I'm working on extracting the needed info from Philips 
right now :> If I can get the info and if we can get parts samples then 
that's the solution I'd like to use.

Brian

-- 
-----------------------------------------------------
Brian C. Lane (W7BCL)                      Programmer
www.shinemicro.com   RF, DSP & Microcontroller Design

Hi Brian, I've been using the 12-bit TI TLC2554 ADC (digikey stock) on
the LPC2106 SPI bus with good results. This LPC2106 code for this 4
channel ADC can run at over 80 KSPS when you've got the core clocked
at close to 60 MHz (using the PLL).  The part is capable of converting
at over 1 MSPS but the limitation in speed is due to the unbuffered
SPI bus on the LPC2100 series. In particular, the LPC2100 code in SPI
Master Mode has to send/recv the SPI data 8 bits at a time, but due to
the fact that some SPI transfers from the TLC2554 require up to
32-bits (multichannel mode) and most require 16 bits, the code has to
monitor the status and this slows things down a bit. I'm looking into
using a Xilinx Coolrunner-II to manage the SPI clock (= ADC clock) and
run the LPC2106 SPI in slave mode. 

Any one else have thoughts on the ADC SPI ?

Russ

--- In lpc2100@yahoogroups.com, "Brian C. Lane" <brian@s...> wrote:
> I'm working on designing a new project where we need to process 9600bps 
> packets (similar to G3RUH format), we'd like to use the LPC2106 which 
> ought to be fast enough. But I'm having trouble coming up with a 
> suitable  ADC. It needs to sample at 48khz, 10 bits are fine, 2 
> channels. It needs to be consistent (no jitter).
> 
> I could use a SPI ADC with the ARM as the SPI master, but I'm afraid 
> that other interrupts in the system will effect the sample accuracy (it 
> will also be doing some serial communications and have some timers 
> running) and introduce jitter into sample rate.
> 
> Ideally the ADC would be a SPI master with its own reference clock, 
> feeding the samples to the ARM with some indication (high bit 
> set/clear?) of which channel the data came from. There are some AKM 
> ADCs/codecs that might work, but their left/right clock would somehow 
> need to be associated with the data -- hard to do if you have a
delay in 

> getting to the interrupt to process the data and L/R has already 
> switched to the other channel.
> 
> Any thoughts?
> 
> Thanks,
> 
> Brian
> 
> -- 
> -----------------------------------------------------
> Brian C. Lane (W7BCL)                      Programmer
> www.shinemicro.com   RF, DSP & Microcontroller Design