68300

Hello everyone,

When you are trying to externally decode signals to develop WE and RD and OE signals, you have to consider multiple cases.  For instance, you have to consider all of the combinations of A0, SIZ1 and SIZ0.  For instance, WE (even) has to assert for all of the following cases:

SIZ1   SIZ0   A0
0        1     x     byte to 8-bit bus    DSACK 1,0  =  1,0
0        1     0     even byte to 16-bit bus    DSACK 1,0  =  0,x
1        0     0     word to 8-bit bus    DSACK 1,0  =  1,0
1        0     0     word to 16-bit bus    DSACK 1,0  =  0,x
1        1     1     3-byte to 8-bit bus    DSACK 1,0  =  1,0
0        0     0     long word to 8 - bit bus    DSACK 1,0  = 1,0  
0        0     0     long word to 16 bit bus    DSACK 1,0  =  0,x



Likewise, WE (odd) has to assert for all the following cases:

SIZ1   SIZ0   A0
0       1     1      odd byte to 16-bit bus    DSACK 1,0  =  0,x
1       0     0      word to 16-bit bus    DSACK 1,0  =  0,x
0       0     0      long word to 16 bit bus    DSACK 1,0  =  0,x


In your equations below, I do not believe that you are decoding for all the cases.  Remember, if you are decoding external signals for WE and RD and you are NOT using the chip selects, it is your responsibility to properly generate the DSACK signals.

Regards,

Charlie





 

-----Original Message-----
From: development [mailto:development@...]
Sent: Friday, February 20, 2004 5:11 AM
To: 68300@yahoogroups.com
Subject: [68300] Chip select timing problem
Importance: High


Hi All, 
      I am using a 68332 interfaced with a memory bank 
comprising of two HM628512 RAMs ( 70 nS). The chip selects 
of the two RAMs are grounded and the OE and WE of the RAMs 
are being controlled by individual chipselects.

CS0  ----> Odd byte Output Enable
CS1  ----> Odd byte Write Enable
CS2  ----> Even byte Output Enable
CS10 ----> Even byte Write Enable

As this is an obvious waste of chip selects and now that I 
am running short of chip selects, I wish to use only one 
chip select in the place of four.


The equations for the OE and WE are as follows

" Even byte Read signal equation
  RDEVEN  =	(!RW) # A0  # (SIZ0 & SIZ1) # CS;


" Even byte Write signal equation
  WREVEN  =	RW # A0  # (SIZ0 & SIZ1) # CS;


" Odd byte Read signal equation
  RDODD   = 	(!RW) # (!A0 & SIZ0) # (SIZ0 & SIZ1) # (A0 
& SIZ1) # (A0 & !SIZ0) # CS;


" Odd byte Write signal equation
  WRODD	= 	RW # (!A0 & SIZ0) # (SIZ0 & SIZ1) # (A0 & 
SIZ1) # (A0 & !SIZ0) # CS;


  The chip enable pin on the RAMs are grounded as usual but 
the problem that I am now facing is that the RAMs do not 
work as expected which probably may be due to some mismatch 
in timing. I am using a Lattice CPLD of 5 nS speed grade to 
implement the above logic. 

  Can any body suggest as to what may be wrong with my 
scheme or the implementation of the logic?

   It would be a great help if anybody could suggest a 
better and alternate way of doing the same.

Thanks & Regards,
Philip Jones,
Engineer,
R&D Department,
ID Technologies. (A division of mark elektriks)
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