Chip select timing problem
2004-02-20 by development
Hi All,
I am using a 68332 interfaced with a memory bank
comprising of two HM628512 RAMs ( 70 nS). The chip selects
of the two RAMs are grounded and the OE and WE of the RAMs
are being controlled by individual chipselects.
CS0 ----> Odd byte Output Enable
CS1 ----> Odd byte Write Enable
CS2 ----> Even byte Output Enable
CS10 ----> Even byte Write Enable
As this is an obvious waste of chip selects and now that I
am running short of chip selects, I wish to use only one
chip select in the place of four.
The equations for the OE and WE are as follows
" Even byte Read signal equation
RDEVEN = (!RW) # A0 # (SIZ0 & SIZ1) # CS;
" Even byte Write signal equation
WREVEN = RW # A0 # (SIZ0 & SIZ1) # CS;
" Odd byte Read signal equation
RDODD = (!RW) # (!A0 & SIZ0) # (SIZ0 & SIZ1) # (A0
& SIZ1) # (A0 & !SIZ0) # CS;
" Odd byte Write signal equation
WRODD = RW # (!A0 & SIZ0) # (SIZ0 & SIZ1) # (A0 &
SIZ1) # (A0 & !SIZ0) # CS;
The chip enable pin on the RAMs are grounded as usual but
the problem that I am now facing is that the RAMs do not
work as expected which probably may be due to some mismatch
in timing. I am using a Lattice CPLD of 5 nS speed grade to
implement the above logic.
Can any body suggest as to what may be wrong with my
scheme or the implementation of the logic?
It would be a great help if anybody could suggest a
better and alternate way of doing the same.
Thanks & Regards,
Philip Jones,
Engineer,
R&D Department,
ID Technologies. (A division of mark elektriks)
============================================================
B1/1, Sai Sahawas Apt., \ufffd|\ufffdPhone: +91-20-4003315, 4007158
Oppo. Corporation Bank, \ufffd|\ufffdTeleFax: +91-20-5410479
Maharshi Karvenagar, \ufffd \ufffd |\ufffdEmail: development@...
Hingne (Bk), \ufffd \ufffd \ufffd \ufffd \ufffd \ufffd | www.markelektriks.com
Pune - 411052. India. \ufffd \ufffd|
============================================================