Lpc2000

Can someone unconfuse me on several I2C issues as I try to understand
the Philips I2C code in the file section?

On, my design using a LPC2148, I am using Master Transmitter mode to
address a RAM.

The AA flag: Is it only used to acknowledge data received from the RAM
after reading from I2C0DAT?  I assume that the ACKs received from the
RAM when simply addressing it is not related to AA (but is the SI
bit).  I noticed in the Philips code that the only AA assertion is
done after receiving data from the chip.  I also assume that the slave
will always give an ACK after sending it data (by the SI flag).  Or,
am I totally off base?

Also, does SCL run all the time, or just during the data transfer? 
I'm not seeing a SCL signal at all when I start my code.

Thanks.

Sutton

--- In lpc2000@yahoogroups.com, "Sutton Mehaffey" <sutton@...> wrote:
>
> Can someone unconfuse me on several I2C issues as I try to understand
> the Philips I2C code in the file section?
> 
> On, my design using a LPC2148, I am using Master Transmitter mode to
> address a RAM.
> 
> The AA flag: Is it only used to acknowledge data received from the RAM
> after reading from I2C0DAT?  I assume that the ACKs received from the
> RAM when simply addressing it is not related to AA (but is the SI
> bit).  I noticed in the Philips code that the only AA assertion is
> done after receiving data from the chip.  I also assume that the slave
> will always give an ACK after sending it data (by the SI flag).  Or,
> am I totally off base?
> 
> Also, does SCL run all the time, or just during the data transfer? 
> I'm not seeing a SCL signal at all when I start my code.
> 
> Thanks.
> 
> Sutton
>

You can get the specifications for the I2C protocol here:
http://www.semiconductors.philips.com/acrobat_download/literature/9398/39340011.pdf

Regarding SCL, the quick answer is that SCL remains high unless there
is an actual transfer in progress. The phasing of SCL and SDA
transitions define the start/stop conditions of the bus. 

-- Dave

--- In lpc2000@yahoogroups.com, "Sutton Mehaffey" <sutton@...> wrote:
>
> Can someone unconfuse me on several I2C issues as I try to understand
> the Philips I2C code in the file section?
> 
> On, my design using a LPC2148, I am using Master Transmitter mode to
> address a RAM.
> 
> The AA flag: Is it only used to acknowledge data received from the RAM
> after reading from I2C0DAT?  I assume that the ACKs received from the
> RAM when simply addressing it is not related to AA (but is the SI
> bit).  I noticed in the Philips code that the only AA assertion is
> done after receiving data from the chip.  I also assume that the slave
> will always give an ACK after sending it data (by the SI flag).  Or,
> am I totally off base?

When the master reads data from the slave it acknowledges by asserting
AA for every byte EXCEPT the last byte.  For the last byte the master
does not assert AA and this is a NAK to the slave which stops the
transaction.  This is done in state 0x50.

I think in EVERY case, the receipient sends the ACK.  When a slave is
first addressed, it is the receipient of the address and it sends the
ACK.  When the master reads data, it sends the ACK for all but the
last byte.  When the master writes data, the receiver sends the ACKs
for every byte, assuming no error.

Figure 34 in the 2148 User Manual indicates which device is talking
and which device is sending ACKs in the case of reading from a device
- Master Receiver mode.

Figure 33 in the manual indicates which device is talking and which
device is sending ACKs in the case of writing to a device - Master
Transmitter mode.

Section 11.9 "Software example" gives a very good description of
exactly what should happen at each state.

> 
> Also, does SCL run all the time, or just during the data transfer? 
> I'm not seeing a SCL signal at all when I start my code.

Both the SCL and SDA idle in the high state.  The master only emits a
clock during a transaction.

It may be useful to take a three 2-input NAND gates and build a
circuit that detects the START condition.  Use 3 gates from a 74LCX00

NAND1 = SDA NAND SDA - just an inverter
NAND2 = SCL NAND NAND1 - forms NOT (SCL AND SDA')  
NAND3 = NAND2 NAND NAND2 - forms (SCL AND SDA')

Trigger your scope on the rising edge of NAND3 or the falling edge of
NAND2.

Richard

Rather than using external gates to trigger the scope, it may be just
as easy to use a spare IO pin and set it when the Start condition is
set by I2C0CONSET=0x20 (or similar).  Then clear the pin upon entry
into the interrupt routine.

I posted a reply similar to this earlier.  It appears to have gotten
lost.  If it shows up, I will delete it.

Richard

Richard,

In my code (that doesn't work yet), I am not using an interrupt.  But,
constantly polling the SI bit.  Is this not a valid way to do it?  If
not, that could be part of my problem.  In this instance, I don't need
to be doing anything while doing I2C, so I thought I would save an
interrupt.

Sutton


--- In lpc2000@yahoogroups.com, "rtstofer" <rstofer@...> wrote:

>
> Rather than using external gates to trigger the scope, it may be just
> as easy to use a spare IO pin and set it when the Start condition is
> set by I2C0CONSET=0x20 (or similar).  Then clear the pin upon entry
> into the interrupt routine.
> 
> I posted a reply similar to this earlier.  It appears to have gotten
> lost.  If it shows up, I will delete it.
> 
> Richard
>

Do you have pull-ups on SCK and SDA lines?


--- In lpc2000@yahoogroups.com, "Sutton Mehaffey" <sutton@...> wrote:
>
> Can someone unconfuse me on several I2C issues as I try to 
understand
> the Philips I2C code in the file section?
> 
> On, my design using a LPC2148, I am using Master Transmitter mode 
to
> address a RAM.
> 
> The AA flag: Is it only used to acknowledge data received from the 
RAM
> after reading from I2C0DAT?  I assume that the ACKs received from 
the
> RAM when simply addressing it is not related to AA (but is the SI
> bit).  I noticed in the Philips code that the only AA assertion is
> done after receiving data from the chip.  I also assume that the 
slave
> will always give an ACK after sending it data (by the SI flag).  
Or,

> am I totally off base?
> 
> Also, does SCL run all the time, or just during the data transfer? 
> I'm not seeing a SCL signal at all when I start my code.
> 
> Thanks.
> 
> Sutton
>

Yes.  I'm using the Embedded Artists 2148 Demo board, in which the
schematic shows pullups.  I'm connecting a RAM chip via their
accessory prototype board, which has direct connections to the I2C bus.

Sutton


--- In lpc2000@yahoogroups.com, "Dezheng Tang" <dtang@...> wrote:

>
> Do you have pull-ups on SCK and SDA lines?
> 
> 
> --- In lpc2000@yahoogroups.com, "Sutton Mehaffey" <sutton@> wrote:
> >
> > Can someone unconfuse me on several I2C issues as I try to 
> understand
> > the Philips I2C code in the file section?
> > 
> > On, my design using a LPC2148, I am using Master Transmitter mode 
> to
> > address a RAM.
> > 
> > The AA flag: Is it only used to acknowledge data received from the 
> RAM
> > after reading from I2C0DAT?  I assume that the ACKs received from 
> the
> > RAM when simply addressing it is not related to AA (but is the SI
> > bit).  I noticed in the Philips code that the only AA assertion is
> > done after receiving data from the chip.  I also assume that the 
> slave
> > will always give an ACK after sending it data (by the SI flag).  
> Or,
> > am I totally off base?
> > 
> > Also, does SCL run all the time, or just during the data transfer? 
> > I'm not seeing a SCL signal at all when I start my code.
> > 
> > Thanks.
> > 
> > Sutton
> >
>

--- In lpc2000@yahoogroups.com, "Sutton Mehaffey" <sutton@...> wrote:
>
> Yes.  I'm using the Embedded Artists 2148 Demo board, in which the
> schematic shows pullups.  I'm connecting a RAM chip via their
> accessory prototype board, which has direct connections to the I2C bus.
> 
> Sutton
> 
> 
What bit rate are you running the I2C bus at?
The open drain I2C bus speed capability depends on the size of the
pull up resistors on the bus, since they determine the rise time with
the bus capacitance. If you are trying to go faster than the bus
resistors can handle, you will encounter bus errors. To debug your
driver logic it would probably be helpful to run the bus at a slow
speed until you are more sure there are no software errors.

-- Dave

120kB

"What bit rate are you running the I2C bus at?"





--- In lpc2000@yahoogroups.com, "derbaier" <dershu@...> wrote:
>
> --- In lpc2000@yahoogroups.com, "Sutton Mehaffey" <sutton@> wrote:
> >
> > Yes.  I'm using the Embedded Artists 2148 Demo board, in which the
> > schematic shows pullups.  I'm connecting a RAM chip via their
> > accessory prototype board, which has direct connections to the I2C
bus.

> > 
> > Sutton
> > 
> > 
> What bit rate are you running the I2C bus at?
> The open drain I2C bus speed capability depends on the size of the
> pull up resistors on the bus, since they determine the rise time with
> the bus capacitance. If you are trying to go faster than the bus
> resistors can handle, you will encounter bus errors. To debug your
> driver logic it would probably be helpful to run the bus at a slow
> speed until you are more sure there are no software errors.
> 
> -- Dave
>

That is a pretty ambitious speed for an untried hardware and software
combination! It may be prudent to drop the speed an order of magnitude
temporarily for debugging? You can estimate the maximum speed of your
I2C bus if you know the pullup resistor value AND the bus capacitance.
The pulse rise time is going to be determined by the product of those
two values, so unless you know them you will need to determine the
maximum speed experimentaly by starting slow and working up. The pulse
fall time will be determined by the 2148's open drain driver's current
capacity, but that is much less likely to be the problem IMHO.

--Dave


--- In lpc2000@yahoogroups.com, "Sutton Mehaffey" <sutton@...> wrote:

>
> 120kB
> 
> "What bit rate are you running the I2C bus at?"
> 
> 
> 
> 
> 
> --- In lpc2000@yahoogroups.com, "derbaier" <dershu@> wrote:
> >
> > --- In lpc2000@yahoogroups.com, "Sutton Mehaffey" <sutton@> wrote:
> > >
> > > Yes.  I'm using the Embedded Artists 2148 Demo board, in which the
> > > schematic shows pullups.  I'm connecting a RAM chip via their
> > > accessory prototype board, which has direct connections to the I2C
> bus.
> > > 
> > > Sutton
> > > 
> > > 
> > What bit rate are you running the I2C bus at?
> > The open drain I2C bus speed capability depends on the size of the
> > pull up resistors on the bus, since they determine the rise time with
> > the bus capacitance. If you are trying to go faster than the bus
> > resistors can handle, you will encounter bus errors. To debug your
> > driver logic it would probably be helpful to run the bus at a slow
> > speed until you are more sure there are no software errors.
> > 
> > -- Dave
> >
>

IOn that system I think only one of the I2C buses has pullups fitted - the other doesn't.   Just checking you're not using the "second" I2C bus on the proto expansion board?

Worth also double checking the bit ordering (LSB or MSB) of any device you're talking to... I've seen people have back-to-front commands apparently "work" - for a little while anyways...  :-)

-- Alex

  ----- Original Message ----- 
  From: Sutton Mehaffey 
  To: lpc2000@yahoogroups.com 
  Sent: Thursday, May 04, 2006 9:34 PM
  Subject: [lpc2000] Re: I2C question


  Yes.  I'm using the Embedded Artists 2148 Demo board, in which the
  schematic shows pullups.  I'm connecting a RAM chip via their
  accessory prototype board, which has direct connections to the I2C bus.

  Sutton


  --- In lpc2000@yahoogroups.com, "Dezheng Tang" <dtang@...> wrote:
  >
  > Do you have pull-ups on SCK and SDA lines?
  > 
  > 
  > --- In lpc2000@yahoogroups.com, "Sutton Mehaffey" <sutton@> wrote:
  > >
  > > Can someone unconfuse me on several I2C issues as I try to 
  > understand
  > > the Philips I2C code in the file section?
  > > 
  > > On, my design using a LPC2148, I am using Master Transmitter mode 
  > to
  > > address a RAM.
  > > 
  > > The AA flag: Is it only used to acknowledge data received from the 
  > RAM
  > > after reading from I2C0DAT?  I assume that the ACKs received from 
  > the
  > > RAM when simply addressing it is not related to AA (but is the SI
  > > bit).  I noticed in the Philips code that the only AA assertion is
  > > done after receiving data from the chip.  I also assume that the 
  > slave
  > > will always give an ACK after sending it data (by the SI flag).  
  > Or,
  > > am I totally off base?
  > > 
  > > Also, does SCL run all the time, or just during the data transfer? 
  > > I'm not seeing a SCL signal at all when I start my code.
  > > 
  > > Thanks.
  > > 
  > > Sutton
  > >
  >







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