Lpc2000

I just added some code to the Rowley LED flasher example to set up the PLL
for 60 MHz operation; it looks as though it is running six times faster,
judging by the LEDs. I filched it from some other code someone sent me that
he's written for his own hardware, based on the Ashling board circuit.
Here's the routine, if anyone else wants to try it:

void initPLL(void)
{
 unsigned char i;

 volatile unsigned long  * vicIntEnClear;
 volatile unsigned char  * pllCON;
 volatile unsigned char  * pllCFG;
 volatile unsigned short * pllSTAT;
 volatile unsigned char  * pllFEED;

       vicIntEnClear  =  (volatile unsigned long  *)0xFFFFF014;
 pllCON   =  (volatile unsigned char  *)0xE01FC080;
 pllCFG   =  (volatile unsigned char  *)0xE01FC084;
 pllSTAT  =  (volatile unsigned short *)0xE01FC088;
 pllFEED  =  (volatile unsigned char  *)0xE01FC08C;

    // Disabling IT
 *vicIntEnClear  = 0xFFFFFFFF;

 // Seting up the PLL frequency

 *pllCFG   = 0x25;  // P = 2, M = 6
 *pllCON   = 0x01;  // Enabling PLL but not connecting it
 *pllFEED  = 0xAA; // Actualising the setting

 for(i=1;i<10;i++);   // waiting

 *pllFEED  = 0x55; // Actualising the setting

 while ( !(*pllSTAT & 0x0400) ) ; // waiting for PLL lock

 // connecting PLL

    *pllCON   = 0x03;  // Enabling PLL but not connecting it
    *pllFEED  = 0xAA; // Actualising the setting
    for(i=1;i<10;i++);   // waiting
    *pllFEED  = 0x55; // Actualising the setting


}


Leon
--
Leon Heller, G1HSM
Email: aqzf13@...
http://www.geocities.com/leon_heller

At 12:22 AM 11/23/03 +0000, you wrote:
>I just added some code to the Rowley LED flasher example to set up the PLL
>for 60 MHz operation; it looks as though it is running six times faster,
>judging by the LEDs. I filched it from some other code someone sent me that
>he's written for his own hardware, based on the Ashling board circuit.
>Here's the routine, if anyone else wants to try it:



>  *pllCFG   = 0x25;  // P = 2, M = 6
>  *pllCON   = 0x01;  // Enabling PLL but not connecting it
>  *pllFEED  = 0xAA; // Actualising the setting
>
>  for(i=1;i<10;i++);   // waiting
>
>  *pllFEED  = 0x55; // Actualising the setting
>
>  while ( !(*pllSTAT & 0x0400) ) ; // waiting for PLL lock
>
>  // connecting PLL
>
>     *pllCON   = 0x03;  // Enabling PLL but not connecting it
>     *pllFEED  = 0xAA; // Actualising the setting
>     for(i=1;i<10;i++);   // waiting
>     *pllFEED  = 0x55; // Actualising the setting
A question Leon.  Why did you put the delay in between the writes to pllFEED?

Heres an alternative (it's what I am using).

void init_pll( void)
  {

         /* set pll divisor, multiplier */
  PLLCFG = 0x25;         /* MSEL = 5 --> M = 6, PSEL = 1 --> P = 2       */
                         /* cclk = M*Fosc = 60,000,000                   */
                         /* Fcco = cclk * 2 * P = 240,000,000            */
         /* enable pll */
  PLLCON = 1;            /* Enables PLL                                  */
  PLLFEED = 0xAA;        /* Change to setting above.  These two updates  */
  PLLFEED = 0x55;        /* MUST occur in sequence on the VPB bus.       */

         /* wait for lock */
  while( (PLLSTAT & 0x400) == 0) {
     }

         /* connect pll */
  PLLCON = 3;            /* Enables and connects PLL                     */
  PLLFEED = 0xAA;        /* Change to setting above.  These two updates  */
  PLLFEED = 0x55;        /* MUST occur in sequence on the VPB bus.       */
  }

Robert Adsett

--- In lpc2100@yahoogroups.com, Robert Adsett <radsett@a...> wrote:

[deleted]

> A question Leon.  Why did you put the delay in between the writes to
pllFEED?


I don't know why this was included. I just tried the code 'as is'. I
can't see why it was included, now you mention it.

Leon

Is it allowed to use a 20MHz osc/crystal with M=3,P=2 to
get a 60MHz cclk?  The docs state that cclk must be an
EVEN multiple of fosc.  Hopefully that really should read
an INTEGER multiple.

Thanks
-Bill Knight
R O SoftWare

At 10:47 AM 12/26/03 -0600, you wrote:
>Is it allowed to use a 20MHz osc/crystal with M=3,P=2 to
>get a 60MHz cclk?  The docs state that cclk must be an
>EVEN multiple of fosc.  Hopefully that really should read
>an INTEGER multiple.

I certainly read that as integer multiple.  Even as opposed to uneven 
rather than even as opposed to odd.  IE 3 goes into 6 evenly.

Maybe that usage of even is restricted to certain dialects of english?

Robert

" 'Freedom' has no meaning of itself.  There are always restrictions,
be they legal, genetic, or physical.  If you don't believe me, try to
chew a radio signal. "

                         Kelvin Throop, III

I certainly hope so.  I am designing a small board but do not have
an LPC eval board to to use to try things out.

Thanks
-Bill

PS - I would appreciate if someone could try out the settings
(M=3, P=2) even w/ the standard 10MHz crystal and see if the LPC
operates as expected.  Thanks again.



On Fri, 26 Dec 2003 11:55:15 -0500, Robert Adsett wrote:

At 10:47 AM 12/26/03 -0600, you wrote:
>Is it allowed to use a 20MHz osc/crystal with M=3,P=2 to
>get a 60MHz cclk?  The docs state that cclk must be an
>EVEN multiple of fosc.  Hopefully that really should read
>an INTEGER multiple.

I certainly read that as integer multiple.  Even as opposed to uneven 
rather than even as opposed to odd.  IE 3 goes into 6 evenly.

Maybe that usage of even is restricted to certain dialects of english?

Robert

At 11:02 AM 12/26/03 -0600, you wrote:
>PS - I would appreciate if someone could try out the settings
>(M=3, P=2) even w/ the standard 10MHz crystal and see if the LPC
>operates as expected.  Thanks again.

Simple enough.

--

It appears to work just fine.  A little hard to tell what the internal 
clock frequency actually is, but serial port seems to work as expected.

Robert

" 'Freedom' has no meaning of itself.  There are always restrictions,
be they legal, genetic, or physical.  If you don't believe me, try to
chew a radio signal. "

                         Kelvin Throop, III

On Fri, 26 Dec 2003 14:36:29 -0500, Robert Adsett wrote:

At 11:02 AM 12/26/03 -0600, you wrote:
>PS - I would appreciate if someone could try out the settings
>(M=3, P=2) even w/ the standard 10MHz crystal and see if the LPC
>operates as expected.  Thanks again.

Simple enough.

--

It appears to work just fine.  A little hard to tell what the internal 
clock frequency actually is, but serial port seems to work as expected.

Robert
===============================================================
Thanks Robert.  I assume you mean the serial port is working at
1/2 the data rate compared to when the PLL was configured with
M=6,P=2 using the same crystal.

-Bill

At 02:42 PM 12/26/03 -0600, you wrote:
>On Fri, 26 Dec 2003 14:36:29 -0500, Robert Adsett wrote:
>
>It appears to work just fine.  A little hard to tell what the internal
>clock frequency actually is, but serial port seems to work as expected.
>
>Robert
>===============================================================
>Thanks Robert.  I assume you mean the serial port is working at
>1/2 the data rate compared to when the PLL was configured with
>M=6,P=2 using the same crystal.
>
>-Bill

Actually my test program corrects the baud rate based on what it thinks the 
CPU frequency is, so since I can still receive the output and it prints 
that it thinks the internal rate is 30MHz....

Hmm, I should be able to fool the timer by setting the cpu clock after it 
inits....

---

That's a little more definitive.  Start up timer with cpu frequency at 
10MHz, then switch CPU freq to 30MHz and use timer to toggle output pin 
every '1 sec'.  Measure high time

High time = 333ms

IE internal clock is 3X what it was when timer was started.

Looks good to me.

Robert

" 'Freedom' has no meaning of itself.  There are always restrictions,
be they legal, genetic, or physical.  If you don't believe me, try to
chew a radio signal. "

                         Kelvin Throop, III

On Fri, 26 Dec 2003 16:14:15 -0500, Robert Adsett wrote:

That's a little more definitive.  Start up timer with cpu frequency at 
10MHz, then switch CPU freq to 30MHz and use timer to toggle output pin 
every '1 sec'.  Measure high time

High time = 333ms

IE internal clock is 3X what it was when timer was started.
====================================================================
Great.  Thanks again for the help.

-Bill

> Is it allowed to use a 20MHz osc/crystal with M=3,P=2 to
> get a 60MHz cclk?  The docs state that cclk must be an
> EVEN multiple of fosc.  Hopefully that really should read
> an INTEGER multiple.


I think the PLL documentation would benefit from a re-write ...

My understanding is as follows:

Cclk (the CPU clock) will be M (an integer value, 1-6) * FOSC

Cclk must lie between 10 MHz and 60 MHz

Fcco will be M * FOSC * 2 * P (an integer value, 2,4,8 or 16)

Fcco must be between 156 MHz and 320 MHz


Am I correct?

If so, can someone explain to me why P is referred to in the documentation
as a divider?


Thanks,

Michael.

----- Original Message ----- 

From: "Michael J. Pont" <Michael.Pont@...>
To: <lpc2100@yahoogroups.com>
Sent: Tuesday, January 06, 2004 3:29 PM
Subject: Re: [lpc2100] PLL


>
> > Is it allowed to use a 20MHz osc/crystal with M=3,P=2 to
> > get a 60MHz cclk?  The docs state that cclk must be an
> > EVEN multiple of fosc.  Hopefully that really should read
> > an INTEGER multiple.
>
>
> I think the PLL documentation would benefit from a re-write ...
>
> My understanding is as follows:
>
> Cclk (the CPU clock) will be M (an integer value, 1-6) * FOSC
>
> Cclk must lie between 10 MHz and 60 MHz
>
> Fcco will be M * FOSC * 2 * P (an integer value, 2,4,8 or 16)
>
> Fcco must be between 156 MHz and 320 MHz
>
>
> Am I correct?
>
> If so, can someone explain to me why P is referred to in the documentation
> as a divider?

Is it a pre-scaler? Makes sense if it just divides by 2, 4 etc.

Leon
--
Leon Heller, G1HSM
Email: aqzf13@...
My low-cost Philips LPC210x ARM development system:
http://www.geocities.com/leon_heller/lpc2104.html