Re: [lpc2000] Re: FLASH errata (bigining to hate LPC)
2004-11-19 by Alex Holden
... I and I suspect everyone else here had trouble understanding what your actual question was amidst all the shouting about Philips making mistakes and the
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2004-11-19 by Alex Holden
... I and I suspect everyone else here had trouble understanding what your actual question was amidst all the shouting about Philips making mistakes and the
2004-11-19 by Gus
... get ... back to ... My concern is that my clock must be preprogramed in philips bootloader!!! That is one of the step in updating philips bootloader
2004-11-19 by Gus
I guess so far no one understood my point! When you use the philips bootloader from your code, you pass (address, data, clock) so far everything seems fine.
2004-11-19 by mahlerweb
Hi, are you working with a pll-multiplier ??? ... byte. ... */ ... */ ... */
2004-11-19 by k10elex
I am using Olimex LPC2106 board with 14.7456Mhz crystal. i am facing problem with the Serial port. i initialise the register for 9600 baudrate but its not
2004-11-19 by dave_albert
Thank you...this is exactly what I was looking for! In my application, the CPU is deeply embedded and is not accessible so it cannot be reset or power cycled.
2004-11-19 by tom_laffey
Richard, Regarding your earlier post, I was thinking in terms of delays added by breakpoints, or now reads. In the code below, I see the dummy read in the
2004-11-19 by Richard
Adding a read of the status register (SPSR) to the ISR solves the problem. Now to figure out why....... Richard ... I ... byte ... went
2004-11-18 by Richard
Here is some code that will invoke the bootloader which will read P0.14 (after you have set it low) and initiate ISP. Richard /* ISP Invocation code –
2004-11-18 by Richard
I am putting togther simple SPI routines using an interrupt. What I am see is that, if I put a breakpoint in the SPI ISR, I see the byte get spit out and the
2004-11-18 by tom_laffey
Hi, This turns out to be what I think is an interesting result. I am maintaining state of each image in flash by clearing bits in a state word. This includes
2004-11-18 by Robert Adsett
Thanks for passing this along. It may be the root of a problem that s been bothering me for some time. There are times when I start to think Philips is
2004-11-18 by Owen Mooney
Yup There shore is ! In the LPC2106 anyway. I dunno about the rest of them. But it requrires a reset of the micro! Use the IAP instructions to erase the first
2004-11-18 by g2100g
You MUST enable the FIFO (by setting U0FCR:0) - See Description of that bit in Table 66 of LPC2106 User Manual. Since other sections of the manual imply that
2004-11-18 by tom_laffey
Martin, 2 s complement can be generated a few ways; I chose the textbook flip the bits and add 1 . Subtracting from 0 as you have done produces the same
2004-11-18 by Robert Adsett
... Inverting and adding 1 is a twos complement negation so I would expect it to be that same. I think you are right though a comparison would be useful. Tom
2004-11-18 by capiman@t-online.de
Endian-Problem ? ... From: To: Sent: Thursday, November 18, 2004 9:42 PM Subject: Re: [lpc2000] Re: Interrupt
2004-11-18 by capiman@t-online.de
Have you compared what value you get with your routine and perhaps load the same with my routine ? Is it really the same ? I see you are doing a +1 at the end
2004-11-18 by Robert Adsett
... That rather worries me. I will give it try and see what it does on my code though (I ve got a few other items to take care of first). I place it in the
2004-11-18 by Leighton Rowe
... point. ... hide it ... Good news...I got communication running alot better after enabling FIFOs (U0FCR = 1) at startup. So far, no Rx & Tx glitches yet.
2004-11-18 by tom_laffey
Hi Robert, Thanks for your reply. I found Martin s checksum code, which is ivt_CRC = 0; for(i = 0;i
2004-11-18 by Robert Adsett
... Well that fits with the speculation of an IIR race condition. Doesn t prove it but it does fit. You may have duplicated what I ve been seeing. ...
2004-11-18 by Leighton Rowe
... just ... the end ... Well after double checking & changing my code to the single IIR read concept, things remained the same. The affected packet I receive
2004-11-18 by Robert Adsett
... I think the only other way it starts is if the checksum over the exception vectors fails. Erasing the first flash sector should do it. I believe someone
2004-11-18 by Robert Adsett
... Take a look at the source for Martin s LPC21ISP. It does the calculation and it should be simple to adapt. Robert Freedom has no meaning of itself.
2004-11-18 by tom_laffey
Hi Robert, Did you ever solve the vector table checksum problem? Like you, I ve tried the algorithm described in the manual (the one you typed below) and the
2004-11-18 by dave_albert
Is there any way to launch the ISP software without having the BSL jumper on? (i.e. does it have an entry point that does not check P0.14?)
2004-11-18 by Robert Adsett
... I belive there are examples in the files section. I know newlib-lpc has an example for uart0 (I have a contribution for uart1 that will be in the next
2004-11-18 by Robert Adsett
... I m confused. Are you complaining about loading an updated boot program or about telling the micro what the clock speed is when it has to program flash?
2004-11-18 by Robert Adsett
... I had a thought. If my speculation about a race condition in IIR is correct it may well explain both our problems. In my case I lose the THRE interrupt
2004-11-18 by haack0815
-- ... I mean not the Plilips bootlader if I understand gus right he has in addition his own bootloader. ... code? ... There is no reverse engineering
2004-11-18 by ggindele
... I thought the boot loader can not be overwritten by a regular flash upload - or is it? So is it just a question putting the bootloader at a specific
2004-11-18 by haack0815
Hi Gus, I can t follow your problems 1. If the 1000 device are unmounted, return them to your disti and get a replacement with the actual bootloader. Here in
2004-11-18 by Gus
passing the clock speed in my code should be enough. I don t want to re-do thier job! Or they program the chips for me before they ship. By the way, does
2004-11-18 by Leighton Rowe
Sorry for the delay guys, Point taken for the answers to 1,2, and 3. Thanks Karl & Robert. ... what I ve ... problem I ... assert if ... Robert, I haven t yet
2004-11-18 by Robert Adsett
... Cost I would expect less than twice the cost of programming the application itself (which obviously must be done anyway). There is a fixed overhead (time
2004-11-18 by Gus
but you pass the clock freq. to the IAP at run time!!! why on earth philips wants you to program thier boot loader then program your boot loader then program
2004-11-18 by aravindar_manikandan
hi, i am in need of UART0/UART1 interrupt example programs. thanks in advance, mani
2004-11-18 by FabioDB
With LPC2106 is there somethig to detect if one or more interrupts was lost? -- FabioDB Altraqua
2004-11-18 by Robert Adsett
... That s certainly the way it s supposed to work (and the way I have done it on real 16550s) but when I do this on an LPC2106 with both transmit and
2004-11-18 by zarozaro
Any recomendations/advices/pros and cons on the Ashling tools? I m interested in Vitra and Pathfinder. Zaro
2004-11-17 by Robert Adsett
... Not only reasonable but necessary (even for ISP). The micro has no way of knowing what the baud rate is (only that it matched it, was that 120bd, 1200bd,
2004-11-17 by lpc2100_fan
For ISP the PLL is not active after a reset. The baudrate can be calculated for a given frequency range. But during runtime, reflashing uses IAP (In
2004-11-17 by Robert Adsett
... Timing, They need to know the speed of the clock so they can determine the timing for programming the flash. IE 6 counts at 20Mhz and 12 counts at 10MHz
2004-11-17 by ggindele
Why is the oscillator frequency needed in the first place? Isn t the interface baud rate detected by the bootloader?
2004-11-17 by Karl Olsen
... No, they are the actual shift registers. U0TSR can be checked with U0LSR bit 6, TEMT. TEMT=0 = U0TSR is shifting out a byte, TEMT=1 = U0TSR is idle.
2004-11-17 by Robert Adsett
... Consider the R/W line an extra address bit if it helps. They don t share the same physical memory. The idea (from the 8250 on) is that since you never
2004-11-17 by Leighton Rowe
Just for clarification on the UART Block Diagram (see UM)... 1. Do U0TSR & U0RSR actually representthe Tx & Rx FIFO buffers? I only see U0TSR & U0RSR
2004-11-17 by Gus
Hello, We had a problem with refalshing the chip untill we upgraded the boot loader to 1.63 (LPC2114) no problems anymore! MY question is that there is a step
2004-11-17 by santosh jha
hi, have any one worked on external RTC PCF8583 using I2C? I need C program for LPC 2106. I am using Keil compiler. Santosh Jha ... Do you Yahoo!? Meet the